Honored ContributorHi all,
During building Nios II/standard or Nios II/full_featured, I have used the clock at 50MHz. According to Altera, the Stratix pro board will have 200 DMIPS speed with 1.17 DMIPS/MHz. Can I assign the clock speed to 160 or 200 MHz. Thanks & regard, Goutam
Honored ContributorYou can certainly try. I currently have 5 NIOS processors in a system running at 160 MHz and have had several run at 200MHz. The problem you will likely run into is meeting timing when you actually compile the firmware in Quartus. A lot of the peripherals will have a hard time running at these speeds. Onchip memory that is allocated using M4K blocks will have a hard time keeping up with these speeds. The FPGA you are using will affect this as well. But by all means, give it a shot.
Honored ContributorHello Jackob,
Kindly, explain more about it. Can you explain that if I am going to change the clock speed from 50 MHz to 160/200 MHz. What are changes required for getting so much of clock speed? thanks & regard, GoutamHonored ContributorIs your board a custom board or are you using one of Altera's development kits?
Honored Contributor<div align='right'><{post_snapback}> (index.php?act=findpost&pid=15429)
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--- Quote End --- Well in the SOPC builder you change the frequency for the clock to whatever you desire. Generate the SOPC system. Then you need to open the Quartus project. From here on out it's going to be some firmware development so if you don't know Verilog or VHDL or AHDL you might just want to call the whole thing off. If you are using a NIOS II development board then they provide you with a 50MHz clock. If you want to increase this frequency, then you will need to use a PLL (Phase Locked Loop). Use the megawizard in the tools menu to create a PLL megafunction. Set the input clock frequency to 50MHz and the output clock frequency to whatever your desired frequency is. Then you need to tie the input of the PLL to the 50MHz clock input pin on the FPGA. Connect the output of the PLL to the clock input of your NIOS system. Compile the quartus project. When it's finished look at the timing analysis section of the compilation report. Any paths highlighted in red are not meeting timing requirements. You can either find out how to fix these issues on your own or just scale your clock speed back to the maximum frequency reported by the timing analyzer. Sorry but it's difficult to go too much in depth here. Specific questions will be easier to answer. If you are not a firmware developer then you might not want to attempt any of this.
Honored ContributorHi Goutam,
Jakob has given excellent advice but if your design doesn't reach the required Fmax there may be a few tweaks that you can try before having to compromise your design. The Timing Advisor gives good advice. Also, under 'Analysis & Synthesis Settings' there is a optimisation for speed/balanced/area. When I was struggling with my Fmax an Altera field engineer suggested setting 'balanced' instead of 'speed'. Surprisingly, this did increase my Fmax. Changing the 'seed' value in the 'Fitter Settings' will also alter the Fmax - sometimes faster, sometimes slower. In my design, none of the above have much more than about a 20% gain in speed. If you want 200MHz and you currently have Fmax of around 70MHz then Jakob is right - forget it. If your Fmax is 150MHz then it might be worth playing with SOPC for a while first. Good luck. Banx.
