Honored Contributor
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--- Quote End --- Well in the SOPC builder you change the frequency for the clock to whatever you desire. Generate the SOPC system. Then you need to open the Quartus project. From here on out it's going to be some firmware development so if you don't know Verilog or VHDL or AHDL you might just want to call the whole thing off. If you are using a NIOS II development board then they provide you with a 50MHz clock. If you want to increase this frequency, then you will need to use a PLL (Phase Locked Loop). Use the megawizard in the tools menu to create a PLL megafunction. Set the input clock frequency to 50MHz and the output clock frequency to whatever your desired frequency is. Then you need to tie the input of the PLL to the 50MHz clock input pin on the FPGA. Connect the output of the PLL to the clock input of your NIOS system. Compile the quartus project. When it's finished look at the timing analysis section of the compilation report. Any paths highlighted in red are not meeting timing requirements. You can either find out how to fix these issues on your own or just scale your clock speed back to the maximum frequency reported by the timing analyzer. Sorry but it's difficult to go too much in depth here. Specific questions will be easier to answer. If you are not a firmware developer then you might not want to attempt any of this.
