The Avalon master interface

both are correct

the left one shows read_n and the right one read

the difference is, that read_n is the inverted read signal, that why there is a little _n suffix for negate

also the left shows waitrequest_n with readdatavalid_n and the right one waitrequest

to understand the difference you might have a look at the avalon specification manual

Both are valid in the Avalon-MM spec: http://www.altera.com/literature/manual/mnl_avalon_spec.pdf

If you are creating your own master component make sure you identify your read (or write) signal as either "read" or "read_n" as a signal type depending on whether you use normal polarity (read) or reverse polarity (read_n). As long as you select the type correctly SOPC Builder will know what to do with that signal when it goes to hook it up to the fabric.

thank you for your suggests!

I have a timing diagram about the Master interface,I am not sure it is right.

the r_address,r_read_n,r_waitrequest are the type of Master interface.

thank you!

You just want a master interface with the following signals?

- r_address

- r_read_n

- r_waitrequest

Seems that your "r_read_n" signals in your diagram should be named "r_read".

If a signals suffix with "_n" that means that signal is active low.

If a signals suffix with "_n" that means that signal is active low.

When the master assert a read command

for "read" signal : it goes from low --> high ==> active high

for "read_n" signal : it goes from high --> low ==> active low