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Altera_Forum's avatar
Altera_Forum
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16 years ago

The Avalon master interface

i meet two timing diagram about the master interface and i think the frist one is right,but the secend one appeared in a lot of datasheets. is there anyone can suggest me? thank you in advanc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

You just want a master interface with the following signals?

- r_address

- r_read_n

- r_waitrequest

Seems that your "r_read_n" signals in your diagram should be named "r_read".