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Altera_Forum
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16 years ago

The Avalon master interface

i meet two timing diagram about the master interface and i think the frist one is right,but the secend one appeared in a lot of datasheets. is there anyone can suggest me? thank you in advanc...
Altera_Forum's avatar
Altera_Forum
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16 years ago

both are correct

the left one shows read_n and the right one read

the difference is, that read_n is the inverted read signal, that why there is a little _n suffix for negate

also the left shows waitrequest_n with readdatavalid_n and the right one waitrequest

to understand the difference you might have a look at the avalon specification manual