Still having strange problems with SRAM and FLASH

I am still dealing with problems of unknown nature on my custom board.

Maybe somebody will have a bright idea how to move forward a little:

My custom board based on Cyclone C6 consist of internal 4k ram (int_ram), external CFI flash, external SRAM (both on the same Avalon tri-state bus).

I have prepared a small hosted C-code to run SRAM memory test and flash some LEDs to show progress and the test results... Code is tested and works ok.

When I build NIOS II to boot from an EPCS controler or an external CFI Flash but execute from int_ram everything is fine. My code works great, goes throug the SRAM memory test routine and test ends with a success. From this experiment I would find:

1. CFI flash is configured correctly because:

- I can erase it, program it and verify it with no errors

- I can store the my code and copiero code there

- I can run copier program from CFI Flash fine

- I can copy code from CFI Flash to int_ram and it works ok

2. My SRAM is configured correctly because:

- my C-code goes through all SRAM addresses and reads 32-bits patterns of aaa.../555... previously written

- my C-code goes through "walking 1s" routine for each SRAM address and it checks out ok.

but...

When I build NIOS II to boot from external CFI Flash and execute from there, my code does not work. It does not matter if I link .rodata and .rwdata partitions to go into int_ram or SRAM - it does not work.

When I build NIOS II to boot from external CFI Flash and execute from external SRAM, my code does not work.

I am confused here: CFI Flash tested ok, SRAM tested ok but when I am trying to run my code hosted in these devices everything falls apart. When am I missing here?

BTW - My code skips first 10k of 1Mb SRAM when operates from the same memory to not overwrite itself but tests whole SRAM memory when operates from int_ram. I have also tried slowing down the cpu clock to avoid SRAM timing issues. Nothing helps.