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originally posted by kerri@Jul 23 2004, 01:35 PM
yeah! --- Quote End ---
Wait Kerri - I made mistake when I was re-checking Avalon document today, not setting up my design files...
I had correctly configured this memory for dynamic alignment from the beginning.
I have referred my mistake to the A0 question posted by Fischer and my not-too-bright response about native alignment I wrote too quickly.
Problem still persists, unfortunatelly.
Dividing clk by 8 eliminated timing issues in my opinion. It proves SRAM and flash work ok separately, my code works with several test with except to booting from CFI and running from SRAM, as in the table bellow:
TEST# clk div .reset .exc .text .rodata.rwdata PASSED?
1 8 EPCS int_ram int_ram int_ram Y
2 8 EPCS SRAM0 SRAM0 SRAM0 Y
3 8 CFI int_ram int_ram int_ram Y
4 8 CFI SRAM0 SRAM0 SRAM0 N
5 8 CFI CFI CFI Int_ram N
As you can see, the code works when I boot from EPCS and link my program to run from SRAM, works also when I boot from CFI and link my program to run from int_ram, but IT DOES not work when I boot from flash and link to run from SRAM.
Any idea what (beside timings) might be causing such strange behaviour?
Honored Contributor
