SRAM in a custom board

Are you exactly sure it's the same interface and timing? If it was it would work.

Since you said you're unfamilar with fpga design I would say try the custom interface if possible (it's a really easy bus to use for connecting generic hardware to).

But if you want to be able to design this fast it may not be the way to go (I'm sure you would need some hardware external to the SOPC to do some conversion between that bus standard and the memory.

G-luck

Thanks for replying.

In fact the custom board has a little bit faster memory than the Nios development board.

I think that is a software problem because I can read and write to the external SRAM (all address memory) with a small C-code in the internal FPGA ram. I've used an oscilloscope to check that the signals really go through.

I use NiosII IDE with a download JTAG cable. Is there any other way to put the .txt .rodata and .rwdata in the external SRAM and check it?

Maybe it is due to a SOPC configuration, but I have selected reset and exception address to the external Sram, and selected "unspecified board" as a target. The sram is conected to the avalon bus as it was in the standard configuration.

I'm going to make a program to turn on a led. With my C-code I will copy the memory address of the internal ram to the Sram, and then programm the .sof file of the fpga and see if it reads the external Sram. It's a little crazy but I don't know what to do.

Make sure when you program the sof onto the device that it doesn't trigger a reset on the sram as well (doubtful it would tie into it unless you did that manually in the fpga design).

You can assign the memory to various addresses (I've never done it personally though) using the segmentation functionality.

Do you not have enought onchip memory resources for what you are trying to do? If you're running out but have enabled all the various methods to shrink the memory footprint, then I'd start there.

Hi people,

I have discovered what was wrong with my SRAM. The small C-code that "verified" the SRAM did read and write consecutive operations, instead of writing all the address lines with the address value and then read and check all the memory map. ( Yes I am a software engineerr http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif

The problem was that I had some address lines cut in my custom board! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/ohmy.gif

Before this I tried to use the option "create an interface to user logic" of the SOPC builder (it use avalon bus) , that is a very easy solution for other memories slower than the original provided by altera.

However there is an strange problem unsolved.. if I put the .rodata and .rwdata in the SRAM, then the programs "works" but the "printf()" not! i.e I can turn on a LED but I can not read any message in the console (JTAG). In any case it doesn&#39;t hang. The other posible memory combination works well. I know that it has no sense, I say it just in case it has already happened to anyone.

More things.. Has anyone tried to programm a flash memory in a custom board without a NIOS2 license?? The Nios2-flash-programmer executes the Quartus 2 programmer with the .sof file "time_limited" and it hangs when it ask something to the user. (because you cannot reply to the Quartus 2 programmer)

And... is it posible to programm a flash memory with a 33Mhz clock? the altera documentation says that below 50Mhz it could fail.

To BadOmen: (sorry for my stupid mistake with the SRAM)

" Make sure when you program the sof onto the device that it doesn&#39;t trigger a reset on the sram as well (doubtful it would tie into it unless you did that manually in the fpga design). "

I have verified that NIOS 2 IDE doesn&#39;t erase the memory if the code is the same than before. Quartus2 programmer never erase it.

"Do you not have enought onchip memory resources for what you are trying to do? If you&#39;re running out but have enabled all the various methods to shrink the memory footprint, then I&#39;d start there."

I have done a interactive web server with MicroC\OS-II and LWIP, so no way to reduce it to less than my maximum onboard chip memory (100kbytes)

Hi,

Can you tell which IP have you used in SOPC with this SRAM CY7C1061AV33 ?

Regards

Hayder