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Altera_Forum
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Honored ContributorSOPC builder
Hello,
I began my project and now I begin to understand all the advantages of the NIOS. I have to plug a CMOS video sensor to my NIOS II evaluation board. Would it be better for me to use the SOPC builder to decalre this new component. Or do I have to connect it myself with the hardware already created by the SOPC (PIO, CPU + SDRAM)? Do you have any advice for me to plug the camera? Thank You. Romain.23 Replies
Altera_ForumHi Nofi,
That is a difficult question to answer without knowing more about your camera/peripheral. Does it have any sort of standard-looking bus interface pins (read/write/address/data)? Is the timing for the peripheral constant for each access or can it vary? Does it have internal memory or is a collection of registers where you repeatedly read a data register to get the images? These will affect whether the best way to hook it up is merely with the component editor and some avalon signals going directly to it (simple), or whether you'll need to design some interface logic (more complex) and then make that a SOPC Builder component, or whether to use a very simple architecture like a collection of PIOs as you mention (very easy, but slow). These sorts of things will infuence the best way to hook it up.. please let us know more about it .- Altera_Forum
Hi Jesse,
So I tell you more about this peripheral: it has a 8 bits output, and for the timings, I have to use bits like HREF (for the horizontal timing) and VSYN (for the vertical). The output is in fact a continuous stream of 8 bits. The timing is always the same, and those signals and are all dependant of a Pixel Clock signal. The chip as no memory, that's why we chose to use the SDRAM available on the evaluation board. In this case, do I have to design the device first, for example, to manage the HREF and VSYN signals? Or are there components that I could use and modify directly? And for an eventual design, would you prefer a Verilog HDL or a VHDL file? Thank you, Regards. - Altera_Forum
Hello again,
Where can I find all the functions to code on the DMA? To create a stream, to access the memory, etc... Thank you. Romain. - Altera_Forum
Hello,
How can I divide a clock in C? Is that possible? Or do I need only to make a temporisation? Thank you. - Altera_Forum
Software only based clock division is not preferable (you won't have a clean clock). Instead I would create a hardware based clock divider that you can program with software (usually you program period in terms of input clock cycles).
- Altera_Forum
Hello BadOmen,
Thank you for your answer. I wonder wether it's possible to make a clock divider with the interval timer of the SOPC? If not, of course I know how to make a clock divider in VHDL, but how can I control it in C after that? I mean for the other components there are libraries already made. But for something I do myself, what kind of functions do I use? Thank you. Romain. - Altera_Forum
If you know vhdl,
1. then you have to make your component with registers accessible via avalon bus 2. import it e.g. with SPOPC Builder "Interface to user logic" 3 .you can access these registers with the standard function IOWR and IORD from your C code, you don`t have to build a driver or library. I´ve made a small sample clock and c program in the following thread http://www.niosforum.com/forum/index.php?a...=st&f=17&t=1503 (http://www.niosforum.com/forum/index.php?act=st&f=17&t=1503) or you can follow the pwm sample from altera. - Altera_Forum
I haven't looked at that PWM yet, but like most PWM circuits you can usually program the period (frequency) and the duty cycle. So the interface is usually a couple of registers that get wired up to Avalon, and the rest is just internal logic that creates the new clock.
As for your idea of creating a clock with a timer..... it will not be clock cycle accurate, and do you really want to be using the processor for creating clocks or processing? So I would recommend Fischer's steps that he outlined. - Altera_Forum
Thank you all for your answers.
Those examples are very helpful, now I can go further in the comprehension. - Altera_Forum
Hello,
No I've made some code. I try to insert a video sensor, behaving as a master port for the avalon in my system. Then I use the signals waitrequest and address. I have little questions about that. When I use the signal address, how can I know what will be those addresses, knowing that in SOPC builder, there are no adresses pre-assigned (as it is a master). And for the waitrequest, is it automatically sent by the avalon bus each time that the peripheral has to wait? I hope I was clear and that you won't be annoyed to help me once again. Thank you. Romain.LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; entity camera2 is port ( --sorties avalon --writedata : out std_logic_vector(7 downto 0); -- avalon bus signal --write_n : out std_logic; --avalon bus signal address : out std_logic_vector(31 downto 0); --entrées avalon waitrequest : in std_logic; --les bus d'avalon nécessaires à un streaming sont: --clk, address, read_n, chipselect, readdata,dataavailable et endofpacket --entrées externes vsyn : in std_logic; href : in std_logic; pclk : in std_logic; data : out std_logic_vector(7 downto 0) ); end; architecture a of camera2 is signal donnees : std_logic_vector(7 downto 0); signal synchro_v : std_logic; signal synchro_h : std_logic; signal clock : std_logic; signal addresse_interne : std_logic_vector(31 downto 0); begin clock<=pclk; synchro_v<=vsyn; synchro_h<=href; process(clock) begin if(synchro_h<='1' AND waitrequest<='1') then data<=donnees; adresse_interne<=adresse_interne+16; else if (synchro_v<='1') then addresse_interne<=(others =>'0'); end if; end if; end process; address<=adresse_interne; end a;
