Forum Discussion
Altera_Forum
Honored Contributor
21 years agoSOPC builder
Hello, I began my project and now I begin to understand all the advantages of the NIOS. I have to plug a CMOS video sensor to my NIOS II evaluation board. Would it be better for me to use the...
Altera_Forum
Honored Contributor
21 years agoHello,
No I've made some code. I try to insert a video sensor, behaving as a master port for the avalon in my system. Then I use the signals waitrequest and address. I have little questions about that. When I use the signal address, how can I know what will be those addresses, knowing that in SOPC builder, there are no adresses pre-assigned (as it is a master). And for the waitrequest, is it automatically sent by the avalon bus each time that the peripheral has to wait? I hope I was clear and that you won't be annoyed to help me once again. Thank you. Romain.LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
entity camera2 is
port (
--sorties avalon
--writedata : out std_logic_vector(7 downto 0); -- avalon bus signal
--write_n : out std_logic; --avalon bus signal
address : out std_logic_vector(31 downto 0);
--entrées avalon
waitrequest : in std_logic;
--les bus d'avalon nécessaires à un streaming sont:
--clk, address, read_n, chipselect, readdata,dataavailable et endofpacket
--entrées externes
vsyn : in std_logic;
href : in std_logic;
pclk : in std_logic;
data : out std_logic_vector(7 downto 0)
);
end;
architecture a of camera2 is
signal donnees : std_logic_vector(7 downto 0);
signal synchro_v : std_logic;
signal synchro_h : std_logic;
signal clock : std_logic;
signal addresse_interne : std_logic_vector(31 downto 0);
begin
clock<=pclk;
synchro_v<=vsyn;
synchro_h<=href;
process(clock)
begin
if(synchro_h<='1' AND waitrequest<='1') then
data<=donnees;
adresse_interne<=adresse_interne+16;
else if (synchro_v<='1') then
addresse_interne<=(others =>'0');
end if;
end if;
end process;
address<=adresse_interne;
end a;