SOPC builder

Hi Jesse,

So I tell you more about this peripheral: it has a 8 bits output, and for the timings, I have to use bits like HREF (for the

horizontal timing) and VSYN (for the vertical). The output is in fact a continuous stream of 8 bits. The timing is always the

same, and those signals and are all dependant of a Pixel Clock signal. The chip as no memory, that's why we chose to use the

SDRAM available on the evaluation board.

In this case, do I have to design the device first, for example, to manage the HREF and VSYN signals? Or are there components that I could use and modify directly?

And for an eventual design, would you prefer a Verilog HDL or a VHDL file?

Thank you,

Regards.