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Altera_Forum
Honored Contributor
Honored ContributorSOPC builder
Hello, I began my project and now I begin to understand all the advantages of the NIOS. I have to plug a CMOS video sensor to my NIOS II evaluation board. Would it be better for me to use the...
Altera_ForumHonored Contributor
Honored ContributorHi Jesse,
So I tell you more about this peripheral: it has a 8 bits output, and for the timings, I have to use bits like HREF (for the horizontal timing) and VSYN (for the vertical). The output is in fact a continuous stream of 8 bits. The timing is always the same, and those signals and are all dependant of a Pixel Clock signal. The chip as no memory, that's why we chose to use the SDRAM available on the evaluation board. In this case, do I have to design the device first, for example, to manage the HREF and VSYN signals? Or are there components that I could use and modify directly? And for an eventual design, would you prefer a Verilog HDL or a VHDL file? Thank you, Regards.
