Something strange with SOPC

Hi all!

After was in correspondence with altera I've decided to return q5.0 and sopc5.0.

Answer on my request was -

the vector setting for the parameters can work with quartusii synthesis. but the component editor has the limitation on this. this is because the parameters can be modified when you instant this component later. so we don't suggest that you use the bit width, so that it can be more flexible in the later usage. this is kind of trade-off in the tool design. currently we follow with this solution. fortunately, this won't hurt the performance of your design.

OH NO ! ? ?????

If you have statemachines you would code something like :

// statemachine definition

//------------------------

parameter [2:0] /* synopsys enum states */

PLL_IL = 3'd0,

PLL_FL = 3'd1,

PLL_RC = 3'd2,

PLL_NC = 3'd3,

PLL_GO = 3'd4;

// define state variable(s)

reg [2:0] /* synopsys enum states */ pll_init_state;

// synopsys state_vector pll_init_state

If i understand that what you have posted here right, then the sopc component editor cannot handle parameter [x:y] but quartus can.

I had a quick look at ALL sources where i had these problems as posted before and ALL have this parameter with [x:y]. Now i understand why i can work with sopc component editor if there are no statemachines in verilog.

Now it is clear, Quartus SOPC has a Bug if the component sources have verilog statemachines.

I hope this BUG gets fixed soon. Altera ????

And for the future ... i wish i would get a clear message that tell why what and where instead of error 3 or 10000 ...

Regards.

Michael Schmitt

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originally posted by mschmitt@Mar 28 2006, 12:30 PM

i had a quick look at all sources where i had these problems as posted before and all have this parameter with [x:y]. now i understand why i can work with sopc component editor if there are no statemachines in verilog.

now it is clear, quartus sopc has a bug if the component sources have verilog statemachines.

i hope this bug gets fixed soon. altera ????

and for the future ... i wish i would get a clear message that tell why what and where instead of error 3 or 10000 ...

michael schmitt

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--- quote end ---

--- Quote End ---

Dear Michael Schmitt!

It is not quite right!

You are able still use statemachines in Verilog.

You should replace parameter[3:0] by parameter without define of width.

That is all!

I agree with you, Sopc should be more verbose.

So, I am not working in Altera and unfortunately I can not fix this problem.

Could you check this - "parameter my_time = 40.78;&#39; in any your HDL source, please?

Has you got error in sopc with this line also?

I have a similar problem. Not only do I get the original poster&#39;s error messages, I also get others. I think I have also found a solution. Here are the messages I get when I try to add some Verilog files to "Create New Component" in SOPC Builder:

-----------------------------------------------

Error: command "quartus_map --generate_hdl_interface=Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v ce_temp_directory/ce_temp_quartus_project" returned 3

Error (10054): Verilog HDL Compiler Directive error at i2c_master_bit_ctrl.v(127): can&#39;t open Verilog Design File "i2c_master_defines.v" File: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v Line: 127

Error (10170): Verilog HDL syntax error at i2c_master_bit_ctrl.v(297) near text ";"; expecting an identifier, or a number, or a system task, or "(", or "{", or unary operator, File: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v Line: 297

Error (10170): Verilog HDL syntax error at i2c_master_bit_ctrl.v(362) near text ":"; expecting an identifier, or a number, or a system task, or "(", or "{", or unary operator, File: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v Line: 362

Error (10170): Verilog HDL syntax error at i2c_master_bit_ctrl.v(365) near text ":"; expecting "endcase", or an identifier, or a number, or a system task, or "(", or "{", or unary operator, File: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v Line: 365

Error (10170): Verilog HDL syntax error at i2c_master_bit_ctrl.v(368) near text ":"; expecting "endcase", or an identifier, or a number, or a system task, or "(", or "{", or unary operator, File: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v Line: 368

Error (10170): Verilog HDL syntax error at i2c_master_bit_ctrl.v(371) near text ":"; expecting "endcase", or an identifier, or a number, or a system task, or "(", or "{", or unary operator, File: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v Line: 371

Error (10112): Ignored module "i2c_master_bit_ctrl" at i2c_master_bit_ctrl.v(129) due to previous errors File: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v Line: 129

Error: Quartus II Analysis & Synthesis was unsuccessful. 7 errors, 4 warnings

Error: Processing ended: Fri Jul 21 16:19:05 2006

Error: Elapsed time: 00:00:01

Error: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v.xml does not exist

-----------------------------

Getting rid of the [:] bit width in the .v files does not get rid of the errors. I have to also move the contents of the file that&#39;s included in the `include directive into each .v file. Weird.

The included file has five `defines in it. That&#39;s all. Moving these five lines to the top of the other three files allows these HDL files to be added to the New Component.