Forum Discussion
Altera_Forum
Honored Contributor
20 years agoSomething strange with SOPC
I tried editing component and then has got error. "Error: command "quartus_map --generate_hdl_interface=C:/projects/NIOS_JPEG/ce_temp_directory/avalon_adv202.v ce_temp_directory/ce_temp_quartus...
Altera_Forum
Honored Contributor
20 years ago --- Quote Start --- originally posted by mschmitt@Mar 28 2006, 12:30 PM i had a quick look at all sources where i had these problems as posted before and all have this parameter with [x:y]. now i understand why i can work with sopc component editor if there are no statemachines in verilog.
now it is clear, quartus sopc has a bug if the component sources have verilog statemachines.
i hope this bug gets fixed soon. altera ????
and for the future ... i wish i would get a clear message that tell why what and where instead of error 3 or 10000 ...
michael schmitt
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--- Quote End --- Dear Michael Schmitt! It is not quite right! You are able still use statemachines in Verilog. You should replace parameter[3:0] by parameter without define of width. That is all! I agree with you, Sopc should be more verbose. So, I am not working in Altera and unfortunately I can not fix this problem. Could you check this - "parameter my_time = 40.78;' in any your HDL source, please? Has you got error in sopc with this line also?