Something strange with SOPC

I have a similar problem. Not only do I get the original poster's error messages, I also get others. I think I have also found a solution. Here are the messages I get when I try to add some Verilog files to "Create New Component" in SOPC Builder:

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Error: command "quartus_map --generate_hdl_interface=Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v ce_temp_directory/ce_temp_quartus_project" returned 3

Error (10054): Verilog HDL Compiler Directive error at i2c_master_bit_ctrl.v(127): can't open Verilog Design File "i2c_master_defines.v" File: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v Line: 127

Error (10170): Verilog HDL syntax error at i2c_master_bit_ctrl.v(297) near text ";"; expecting an identifier, or a number, or a system task, or "(", or "{", or unary operator, File: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v Line: 297

Error (10170): Verilog HDL syntax error at i2c_master_bit_ctrl.v(362) near text ":"; expecting an identifier, or a number, or a system task, or "(", or "{", or unary operator, File: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v Line: 362

Error (10170): Verilog HDL syntax error at i2c_master_bit_ctrl.v(365) near text ":"; expecting "endcase", or an identifier, or a number, or a system task, or "(", or "{", or unary operator, File: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v Line: 365

Error (10170): Verilog HDL syntax error at i2c_master_bit_ctrl.v(368) near text ":"; expecting "endcase", or an identifier, or a number, or a system task, or "(", or "{", or unary operator, File: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v Line: 368

Error (10170): Verilog HDL syntax error at i2c_master_bit_ctrl.v(371) near text ":"; expecting "endcase", or an identifier, or a number, or a system task, or "(", or "{", or unary operator, File: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v Line: 371

Error (10112): Ignored module "i2c_master_bit_ctrl" at i2c_master_bit_ctrl.v(129) due to previous errors File: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v Line: 129

Error: Quartus II Analysis & Synthesis was unsuccessful. 7 errors, 4 warnings

Error: Processing ended: Fri Jul 21 16:19:05 2006

Error: Elapsed time: 00:00:01

Error: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v.xml does not exist

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Getting rid of the [:] bit width in the .v files does not get rid of the errors. I have to also move the contents of the file that's included in the `include directive into each .v file. Weird.

The included file has five `defines in it. That's all. Moving these five lines to the top of the other three files allows these HDL files to be added to the New Component.