Slow kernel boot-up (and slow SDRAM read transfer)

I am running a uClinux kernel from DDR2 SDRAM on a Cyclone II DSP Dev. Board.

I was having problems with slow boot-up previously when using Quartus 5.0.

I edited the em_epcs.pm and class.ptf file for EPCS by changing all instance of "extradelay = 1" to "extradelay = 0". This worked and lowered my boot time from about 2 min to under 10 seconds.

I just recently upgraded to Quartus 6.1. The em_epcs.pm and class.ptf files already had the "extradelay = 0" fix in them when installed. But now I'm back to a 90 second boot up time.

This slow boot time may or may not be related to a problem I have encountered when trying to perform pipelined reads from SDRAM with a custom-made master port in my Nios core. The time between reads is 8 26.25MHz clock cycles (at most I believe there should be 1 clock cycle between reads).

With Quartus 6.1 you can choose to pipeline any of the clocks in the Nios core. I pipelined the ddr2_clk that the SDRAM component runs off of but this didn't seem to make a difference to either problem.

Has anyone had similar problems - a slow boot up for your kernel or slow response from SDRAM read transfers??

Any help would be appreciated. Thanks