Forum Discussion
Altera_Forum
Honored Contributor
19 years agoSlow kernel boot-up (and slow SDRAM read transfer)
I am running a uClinux kernel from DDR2 SDRAM on a Cyclone II DSP Dev. Board. I was having problems with slow boot-up previously when using Quartus 5.0. I edited the em_epcs.pm and class.pt...
Altera_Forum
Honored Contributor
19 years agoThe current PIPELINE in SOPC is NO GOOD.
It induced a long latency. Try remove all the PIPELINE.