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Altera_Forum
Honored Contributor
Honored ContributorSlow kernel boot-up (and slow SDRAM read transfer)
I am running a uClinux kernel from DDR2 SDRAM on a Cyclone II DSP Dev. Board. I was having problems with slow boot-up previously when using Quartus 5.0. I edited the em_epcs.pm and class.pt...
Altera_ForumHonored Contributor
Honored ContributorMy original design had no pipelining in SOPC. I added the pipeline when I saw this problem. So neither way is working for me.
