Slow kernel boot-up (and slow SDRAM read transfer)

I am still having problems with the kernel taking over 90 seconds to boot...but it's not essential that it be any faster so I'm not worrying about it for now.

HOWEVER, I am also still having problems reading data out of SDRAM fast enough. I need to read 1 64-bit word every clock cycle (26.25MHz). If I wait for the read_data_valid signal, I get 1 word every 8 clock cycles.

I created an avalon master port to perform pipelined master read transfers to retrieve the data from the DDR2 SDRAM on the Cyclone II DSP Board. I believe the problem lies somewhere in my state machine to control the master read transfer. I have read all the documentation i can find on how to do master read transfers but can't find my problem.

Does anyone have some example code they'd be willing to share?? Thanks.