Forum Discussion
Honored ContributorSGDMA debug
Hello,
I am trying to learn how to use SGDMA to transfer data to memory. First of all, I am trying to connect SGDMA TX directly to SGDMA RX and check results. You can find the source code ->here<- (http://www.codeupload.com/4051) (I've edited the code found on forum, so thanks the guy who provided it). In order to check what is written to the memory, I've connected the SGDMA modules to ONCHIP memory (size: 32768 bytes) and enabled memory content reader on the on-chip memory options. You can see my connections ->here<- (http://i51.tinypic.com/1zz6fj5.png). The problem is that this dma design doesn't work. The data I get is corrupted. I've tried to disconnect cpu.instruction_master and cpu.data_master from onchip memory, then the memory start address goes to 0x00, but results are the same. If I connect the DMA to the DDR memory, then the data passes correctly, Screenshot is ->here<- (http://i53.tinypic.com/2heak61.png). Now why I get this situation: either I try to read or write from/to onchip memory or DDR memory, the core always tries to read/write from/to address 0x800xxxxx. Obviously when it is connected to DDR ram it works, but when to onchip ram it doesn't. Why is this happening? Nios memory bus bugs? How can I check what is written to the memory? If I use only onchip memory for the whole system and DMA it also works fine, but I want a clear vision without Nios stuff in the memory. Thanks.55 Replies
Altera_ForumSGDMA is capable of 19.2Gbps afaik, so the bottleneck is Your memory speed. Default SDRAM chip is capable of 100MHz * 16bit = 1.6Gbps. The wrong content could be wrong transfer technique.
- Altera_Forum
To get decent performance from the SGDMA you need to have to either have a lot of descriptors chained together or have each descriptor perform a lot of accesses. Unfortunately the SGDMA is limited to 64kB sized transfers so that kinda leaves you with the requirement to chain a bunch of descriptors together.
- Altera_Forum
I am trying to use the ST-to-MM SGDMA in my design,writing the ADC data to DDR2 SDRAM and then stream out via ethernet. The DDR2 SDRAM is also used for nios ii core. The ST source is data from external ADC. The descriptors are sotred on an on-chip memory.
Now a question really confused me: 1. with no signal on input of ADC, the data read from ddr2 is about 0x80,which is offset binary,means 0 V, and the SGDMA status register is 0x0C; 2. with signal on input of ADC, only several datas are transmitted and the SGDMA is busy ,the SGDMA status register is 0x14. PS: Attached is my connections in Qsys, and the adc_1 is a component I created. Any advice? Thank you in advance. - Altera_Forum
SGDMA input is not connected? Also I see a bunch of adapters. I'd offer to create a component that wouldn't need such adapters at all.
How frequently ADC gives results? If it's 50MHz 8bit ADC, then You probably have no chances to do packet sending from Nios... - Altera_Forum--- Quote Start --- SGDMA input is not connected? --- Quote End --- Yes, it's connected, since when I click the '-' before a component the connections disappear. --- Quote Start --- How frequently ADC gives results? --- Quote End --- it's 200MHz 8bit ADC. Now I'll try 150MHz, since the frequency of ADC is adjustable.
- Altera_Forum
Nios II will struggle to move this data over Ethernet if you use TCP even if the input rate is 150MHz. Have you seen this?
http://www.alterawiki.com/wiki/nios_ii_udp_offload_example I've seen that design hit 1Gbps line rates. - Altera_Forum
It can't transmit the ADC data and the busy bit of SGDMA status register is set as 1.
The first step is constructing a adc-to-ddr2-to-ethernet data path, regardless of the speed. But it's blocked again and again. Any advice,please. - Altera_Forum
How are you setting up your descriptor chains? Are you using the parked feature of the SGDMA by any chance to do something like ping pong buffering of the ADC data? If so I would start looking there as that feature can have race conditions if Nios II modifies the descriptor chain at the wrong time.
Also I would copy your code fragments into this thread showing how you are accessing the SGDMA (put the code tags around them so that the formatting will be retained). - Altera_Forum
Thanks for your reply. The code fragments is ->here<- (http://codeupload.com/5202).
The descriptor chain is stored on on-chip memory, and no parked feature of SGDMA. I want to use a command received via UART port or a push on a key to trigger a transmission, as you can see two flags in the code, RS232_Rx_flag and key_flag . - Altera_Forum
Nothing jumps out at me that looks incorrect; however, I haven't used this SGDMA in ages so I might have missed something.
It might be worth instrumenting your code for test to that it doesn't wait for commands to come in over RS232 so that you can kick off your code in a simulation and watch how the SGDMA behaves. Things that can cause the SGDMA to become stuck busy: 1) Not terminating the descriptor chain (it looked fine how you did this though) 2) Your ADC is not asserting the ready bit causing the SGDMA to get stuck twiddling its thumbs 3) The SGDMA never properly started (I didn't see anything to suggest this from your code though)
