I am trying to use the ST-to-MM SGDMA in my design,writing the ADC data to DDR2 SDRAM and then stream out via ethernet. The DDR2 SDRAM is also used for nios ii core. The ST source is data from external ADC. The descriptors are sotred on an on-chip memory.
Now a question really confused me:
1. with no signal on input of ADC, the data read from ddr2 is about 0x80,which is offset binary,means 0 V, and the SGDMA status register is 0x0C;
2. with signal on input of ADC, only several datas are transmitted and the SGDMA is busy ,the SGDMA status register is 0x14.
PS: Attached is my connections in Qsys, and the
adc_1 is a component I created.
Any advice? Thank you in advance.