Set initial value at beginning

--- Quote Start ---

I am using the Deo Nano SoC and I want to initialize some register values at startup without hitting a reset button. If there is a way to do this, please show me. I need this for run time and not simulation.

--- Quote End ---

You don't really say in what context you want to do this. Is this in the FPGA logic section (or the CPU complex)? And do you use Verilog or VHDL?

That being said, what you ask for is simple to do in Verilog for logic that can be synthesized (and simulated). An example:

    // PowerUP Reset Logic
    // generate a 500ms reset pulse on initial powerup
    reg    pup_count = 25'd0;
    reg          pup_reset = 1'b1;
    always @(posedge CLOCK_50)
    begin
    pup_count <=# TPD pup_count + 1'd1;
    if (pup_count == 25'd25000000) pup_reset <=# TPD 1'b0;
    end
    wire         reset = pup_reset;

The syntax 'reg id = constant;' is all you need to do to get the configured powerup value of the register to be set to that constant.

For this question, Verilog is good and I am working on the FPGA side. I did not want to pick a language and scare off ~1/2 of my answer base.

I have read in some discussions that something like

reg [31:0] a_word = 32'd123;

is only good for simulation and the value "123" gets ignored when it is put in a .sof file to load in the FPGA for synthesizing.

The syntax 'reg id = constant;' is all you need to do to get the configured powerup value of the register to be set to that constant.

--- Quote End ---

--- Quote Start ---

For this question, Verilog is good and I am working on the FPGA side. I did not want to pick a language and scare off ~1/2 of my answer base.

I have read in some discussions that something like

reg [31:0] a_word = 32'd123;

is only good for simulation and the value "123" gets ignored when it is put in a .sof file to load in the FPGA for synthesizing.

The syntax 'reg id = constant;' is all you need to do to get the configured powerup value of the register to be set to that constant.

--- Quote End ---

Initialization of a register's default state at powerup has worked like this for quite a while in Quartus. The way they do it is that the register is still physically set to zero on configuration / powerup, but the tool essentially adds NOT gates to the D input and Q output of the register, inverting its effective value, and making it appear that the register is set to a one on configuration (ie, in other words they implement the register value using active low logic instead of active high). The 'added' NOT gates will not be left as such, but will (usually) be optimized away into the logic around the register, so they will in most cases effectively disappear. So they usually cost nothing in terms of added resources or delay.