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Altera_Forum
Honored Contributor
8 years agoFor this question, Verilog is good and I am working on the FPGA side. I did not want to pick a language and scare off ~1/2 of my answer base.
I have read in some discussions that something like reg [31:0] a_word = 32'd123; is only good for simulation and the value "123" gets ignored when it is put in a .sof file to load in the FPGA for synthesizing. The syntax 'reg id = constant;' is all you need to do to get the configured powerup value of the register to be set to that constant. --- Quote End ---