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For this question, Verilog is good and I am working on the FPGA side. I did not want to pick a language and scare off ~1/2 of my answer base.
I have read in some discussions that something like
reg [31:0] a_word = 32'd123;
is only good for simulation and the value "123" gets ignored when it is put in a .sof file to load in the FPGA for synthesizing.
The syntax '
reg id = constant;' is all you need to do to get the configured powerup value of the register to be set to that constant.
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Initialization of a register's default state at powerup has worked like this for quite a while in Quartus. The way they do it is that the register is still physically set to zero on configuration / powerup, but the tool essentially adds NOT gates to the D input and Q output of the register, inverting its effective value, and making it appear that the register is set to a one on configuration (ie, in other words they implement the register value using active low logic instead of active high). The 'added' NOT gates will not be left as such, but will (usually) be optimized away into the logic around the register, so they will in most cases effectively disappear. So they usually cost nothing in terms of added resources or delay.
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