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I am using the Deo Nano SoC and I want to initialize some register values at startup without hitting a reset button. If there is a way to do this, please show me. I need this for run time and not simulation.
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You don't really say in what context you want to do this. Is this in the FPGA logic section (or the CPU complex)? And do you use Verilog or VHDL?
That being said, what you ask for is simple to do in Verilog for logic that can be synthesized (and simulated). An example:
// PowerUP Reset Logic
// generate a 500ms reset pulse on initial powerup
reg pup_count = 25'd0;
reg pup_reset = 1'b1;
always @(posedge CLOCK_50)
begin
pup_count <=# TPD pup_count + 1'd1;
if (pup_count == 25'd25000000) pup_reset <=# TPD 1'b0;
end
wire reset = pup_reset;
The syntax '
reg id = constant;' is all you need to do to get the configured powerup value of the register to be set to that constant.
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