SDRAM vs. DDRAM Performance

Some info can be found in followong graph : testresults (http://users.pandora.be/svhb/test%20results%20jpeg%20algorithm.pdf)

Some explanations about the graph :

CPU 85 PM DDR MTXA130 DM DDR MTXA130 means :

CPU 85 : cpu speed 85Mc,

PM DDR MTX 130 = program memory DDR Microtronix core 130Mc

DM DDR MTXA130 = data memory (stack, ...) DDR Microtronix core 130Mc

All CPUs on 52Mc are NIOSII in a cyclone device

All others are NIOSII in CycloneII

The CPU is generated as standard (s-version), with smalles possible instruction cache, no data cache (we want to test memory access here!).

The algorithme is a JPEG encoder, the different steps in the encoding are measured also. No Hardware optimisations!

Synchronuous SRAM seems to be best, but more expensive.

Hope this helps.

Stefaan

Stefaan:

Thanks! That's great information.

I found it interesting that:

CPU 52 PM SDRAM MTX150 DM SDRAM MTX150

did worse than:

CPU 52 PM SDRAM Alt52 DM SDRAM Alt52

-Brian

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originally posted by bgrattan@Sep 18 2006, 04:52 PM

stefaan:

thanks! that's great information.

i found it interesting that:

cpu 52 pm sdram mtx150 dm sdram mtx150

did worse[/b] than:

CPU 52 PM SDRAM Alt52 DM SDRAM Alt52

-Brian

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[/b]

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Yes, that&#39;s funny. But i think the reason is the different clock. CPU with 52Meg and Ram with 150Meg..... there you need Clock-crossings...

Maybe Stefaan can do some more Benchmarks with same frequencys....

Unfortunately there is no comparision between the same frequency like

CPU100 PM SDRAM Alt100 DM SDRAM Alt100 32bit vs. CPU100 DDRAM Alt100 DM DDR Alt100 16bit

Bye

Marco

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originally posted by svhb@Sep 18 2006, 03:17 PM

some info can be found in followong graph : testresults (http://users.pandora.be/svhb/test%20results%20jpeg%20algorithm.pdf)

some explanations about the graph :

cpu 85 pm ddr mtxa130 dm ddr mtxa130 means :

cpu 85 : cpu speed 85mc,

pm ddr mtx 130 = program memory ddr microtronix core 130mc

dm ddr mtxa130 = data memory (stack, ...) ddr microtronix core 130mc

all cpus on 52mc are niosii in a cyclone device

all others are niosii in cycloneii

the cpu is generated as standard (s-version), with smalles possible instruction cache, no data cache (we want to test memory access here!).

the algorithme is a jpeg encoder, the different steps in the encoding are measured also. no hardware optimisations!

synchronuous sram seems to be best, but more expensive.

hope this helps.

stefaan

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=18322)

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@Stefaan

What DDR-Interface was that? 16bit? What SDR-Interface? Also 16bit or 32bit?

Can you tell me more details about the hardware?

Thanx

Marco

If you want to gain decent performance when crossing clock domains, you ought to consider the Avalon to Avalon Bridges project (http://http://www.niosforum.com/pages/project_details.php?p_id=85&t_id=18).

Use the asynchronous FIFOed option.

Cheers,

- slacker

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originally posted by slacker@Sep 19 2006, 10:31 AM

if you want to gain decent performance when crossing clock domains, you ought to consider the avalon to avalon bridges project (http://http://www.niosforum.com/pages/project_details.php?p_id=85&t_id=18).

use the asynchronous fifoed option.

cheers,

- slacker

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=18351)

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Hi slacker,

have you tested these things? There is a thread were someone says it doesn&#39;t work (MSchmitt, i think)....

Thanx

Marco

Hi Marco,

dallasc did the statement that these bridges have problems and longshot answered that he will look into that.

Well i am still looking foreward to use these bridges, but currently no time and i am not shure when i shall use which bridge.

I would like to speed up nios and sdram.

one bridge should connect to all slaves but i still need all 32 int&#39;s

one bridge should connect between all the other masters and the sdram.

still not shure how to setup these bridges for my design.

Michael

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originally posted by mschmitt@Sep 20 2006, 03:57 AM

hi marco,

dallasc did the statement that these bridges have problems and longshot answered that he will look into that.

well i am still looking foreward to use these bridges, but currently no time and i am not shure when i shall use which bridge.

i would like to speed up nios and sdram.

one bridge should connect to all slaves but i still need all 32 int&#39;s

one bridge should connect between all the other masters and the sdram.

still not shure how to setup these bridges for my design.

michael

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=18361)

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Hi Michael,

can we Mail together about SDRAM Performance? I think we have the same problems.

Please contact me under: [email protected]

If you are German then in Deutsch http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/rolleyes.gif

Thanx

Marco

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originally posted by mabcom@Sep 19 2006, 04:04 PM

@stefaan

what ddr-interface was that? 16bit? what sdr-interface? also 16bit or 32bit?

can you tell me more details about the hardware?

thanx

marco

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=18348)

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Cyclone II demo board for DDR-SDRAM (16 bit bus).

Own development for SDRAM (32 bit databus).

I know there could be more comparisons done, but this was it at the time I investigated some memory technologies.

the MTX core at higher speed is indeed slower due to the clock domain crossing.

Stefaan

Your DDR is going to give you higher performance. However, implementing the core is not as straightforward as the regular SDRAM core. There is no reason to go to a 32-bit wide DDR chip because the DDR 16-bit wide interface gives you 32-bits on every clock cycle anyway.

Are you going to do a PLL based core or a DQS based core?

Jake