Some info can be found in followong graph : testresults (http://users.pandora.be/svhb/test%20results%20jpeg%20algorithm.pdf)
Some explanations about the graph :
CPU 85 PM DDR MTXA130 DM DDR MTXA130 means :
CPU 85 : cpu speed 85Mc,
PM DDR MTX 130 = program memory DDR Microtronix core 130Mc
DM DDR MTXA130 = data memory (stack, ...) DDR Microtronix core 130Mc
All CPUs on 52Mc are NIOSII in a cyclone device
All others are NIOSII in CycloneII
The CPU is generated as standard (s-version), with smalles possible instruction cache, no data cache (we want to test memory access here!).
The algorithme is a JPEG encoder, the different steps in the encoding are measured also. No Hardware optimisations!
Synchronuous SRAM seems to be best, but more expensive.
Hope this helps.
Stefaan