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Altera_Forum
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11 years ago

SDRAM signals managing

Hi,

I'm using qsys to implement a system on Quartus II.

I use a DE0-NANO board and I want to access the SDRAM. I want to access it from a Nios II (and also from the hardware design but it's another problem) so I've instantiated a SDRAM controller in qsys, it's configured like this: 32-bit wide, 1 chip select, 2 banks, 14 rows, 8 columns. I don't understand it precisely. It tells it's 32 MBytes-wide. There's a s1 port that I connect to the cpu and a "wire" port. I don't understand what it is. I exported it as I'd like to connect it to the sram pins but it tells I have a 14-bit address port, a cas, a ras and a ba so it seems to me I can only write 2^17 bytes and not 32M. Please tell me how it works.

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  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Frequency doesn't seem to be critical: signals change at a rate of ~1MHz and I just need to be sure to capture every modification. So (3) seems to interest me most (surely because I'm lazy!).

    Only I still don't understand what an Avalon-MM is. Is this only an interface (to what?) or a complete component ?
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Frequency doesn't seem to be critical: signals change at a rate of ~1MHz and I just need to be sure to capture every modification.

    --- Quote End ---

    Um, 1MHz is 1 million changes per second, so you are not going to read that via JTAG and get every transition! At 1MHz you will need a synchronous clock to capture the data changes, or you will need a faster clock, eg., 10MHz, and create a state machine that "looks" for changes in your 4-bit signal.

    --- Quote Start ---

    So (3) seems to interest me most (surely because I'm lazy!).

    --- Quote End ---

    I don't think it will work for 1MHz signal changes.

    --- Quote Start ---

    Only I still don't understand what an Avalon-MM is. Is this only an interface (to what?) or a complete component ?

    --- Quote End ---

    Avalon is just Altera's name for a bus interface protocol. There is a memory mapped definition (Avalon-MM) and a streaming definition (Avalon-ST). You need to read the Altera Qsys documentation, the Altera Avalon Specification, and look at some tutorials.

    Why don't you start by using SignalTap II with a 10MHz clock and capture a 1000 clock periods of data. That should correspond to 100 changes in your GPIO. Post a zoomed section so that we can see the logic changes, and then we can suggest interface options.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    Um, 1MHz is 1 million changes per second, so you are not going to read that via JTAG and get every transition! At 1MHz you will need a synchronous clock to capture the data changes, or you will need a faster clock, eg., 10MHz, and create a state machine that "looks" for changes in your 4-bit signal.

    --- Quote End ---

    I thought of using the 50MHz clock from DE0-nano board for all the design. Don't you think it's enough?

    I DO look at the changes and record it when required.

    --- Quote Start ---

    I don't think it will work for 1MHz signal changes.

    --- Quote End ---

    So, what would you suggest?

    --- Quote Start ---

    Why don't you start by using SignalTap II with a 10MHz clock and capture a 1000 clock periods of data. That should correspond to 100 changes in your GPIO. Post a zoomed section so that we can see the logic changes, and then we can suggest interface options.

    --- Quote End ---

    I don't know SignalTap II but I'll learn to use it. Do you know a starting tutorial I could use?