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Altera_Forum
Honored Contributor
Honored ContributorSDRAM signals managing
Hi, I'm using qsys to implement a system on Quartus II. I use a DE0-NANO board and I want to access the SDRAM. I want to access it from a Nios II (and also from the hardware design but it's anot...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Um, 1MHz is 1 million changes per second, so you are not going to read that via JTAG and get every transition! At 1MHz you will need a synchronous clock to capture the data changes, or you will need a faster clock, eg., 10MHz, and create a state machine that "looks" for changes in your 4-bit signal. --- Quote End --- I thought of using the 50MHz clock from DE0-nano board for all the design. Don't you think it's enough? I DO look at the changes and record it when required. --- Quote Start --- I don't think it will work for 1MHz signal changes. --- Quote End --- So, what would you suggest? --- Quote Start --- Why don't you start by using SignalTap II with a 10MHz clock and capture a 1000 clock periods of data. That should correspond to 100 changes in your GPIO. Post a zoomed section so that we can see the logic changes, and then we can suggest interface options. --- Quote End --- I don't know SignalTap II but I'll learn to use it. Do you know a starting tutorial I could use?
