SDRAM signals managing

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Frequency doesn't seem to be critical: signals change at a rate of ~1MHz and I just need to be sure to capture every modification.

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Um, 1MHz is 1 million changes per second, so you are not going to read that via JTAG and get every transition! At 1MHz you will need a synchronous clock to capture the data changes, or you will need a faster clock, eg., 10MHz, and create a state machine that "looks" for changes in your 4-bit signal.

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So (3) seems to interest me most (surely because I'm lazy!).

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I don't think it will work for 1MHz signal changes.

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Only I still don't understand what an Avalon-MM is. Is this only an interface (to what?) or a complete component ?

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Avalon is just Altera's name for a bus interface protocol. There is a memory mapped definition (Avalon-MM) and a streaming definition (Avalon-ST). You need to read the Altera Qsys documentation, the Altera Avalon Specification, and look at some tutorials.

Why don't you start by using SignalTap II with a 10MHz clock and capture a 1000 clock periods of data. That should correspond to 100 changes in your GPIO. Post a zoomed section so that we can see the logic changes, and then we can suggest interface options.

Cheers,

Dave