Running NIOS program from external SDRAM

Things work correctly when residing in on chip memory because the memory should be populated with code prior to reset and/or on power-up.

When using off chip SDRAM, you should locate your code in a non-volatile memory (flash of some sort) as "payload" for a boot loader that gets automatically programmed into flash when you're using the Nios II IDE and Nios II flash programmer. In this case, the reset address should be pointed at the flash memory. When the Nios II boots, it starts executing from the flash memory running the boot copier/loader which copies the code into SDRAM. When finished, it jumps to that code in SDRAM.

Cheers,

slacker

Thanks for the reply Slacker.

My next question is how would I implement this?

I am using a DE0-nano board which has EEPROM and an EPCS64 serial configuration device which I could use to store the code at first . I can load the NIOS II program there but how do I then point the reset address to it?

How would I create this boot copier/loader and get it to start copying the code to the SDRAM when the NIOS starts? . Would I need to write start up code?

I have wrote code for physical MCUs before and I know that a linker script is required to memory map the sections for the MCU and then some start-up assembler code which runs from the reset address which then jumps to main(). Are these created automatically by the Nios IDE or how does it work?

Thanks,

Paul

Hi Paul

The reset address must point to the EPCS base address.

With EPCS64 you can use the standard bootloader which will take care to copy code to sdram. Everything is done automatically and you'll find your application program ready to run at main entry point.

You need to write a custom bootloader only if you need special features, like loading multiple boot images or remote fpga update.

How do I point the reset address to the EPCS address? There is no option in Qsys.

Will the standard bootloader copy the code to the on-chip RAM or the external SDRAM? Must I modify it to tell it somehow?

Thanks

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How do I point the reset address to the EPCS address? There is no option in Qsys.

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You have to set it in Nios component properties

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Will the standard bootloader copy the code to the on-chip RAM or the external SDRAM? Must I modify it to tell it somehow?

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IIRC this is automatic, unless you have several code sections distributed across different memory devices.

If you configure the linker options to place all code sections in sdram (or sram, or whatever), you don't have to worry about.

Guys,

I'm working through this same situation. I am about 90% there, but still a little foggy on this process. I can get a design to boot from flash by setting the reset vector to flash. I do have a few more questions though.

1. Does the nios ii exception vector point to on chip memory or also point to flash?

2. Am I correct in setting my hal.linker section in the bsp editor to the sdram controller? Below is a screenshot of my settings

https://www.alteraforum.com/forum/attachment.php?attachmentid=9831

3. Under the linker script tab do I set all of the sections to sdram or just .heap and .stack? Below is another screen shot of the settings I'm talking about.

https://www.alteraforum.com/forum/attachment.php?attachmentid=9832

For some reason I still can't get my c-code running with this configuration. Anything obvious I'm missing?

Nios II reset vector must always point to the boot device.

Exception vector can point anywhere but I recommend to use a convenient on-chip memory for faster reaction.

In the linker settings, .reset and .exception MUST match Nios II settings you used in Qsys:

then, sdram is wrong; you should have epcs (or your specific flash device) at the .reset line.