Honored Contributor
Honored ContributorGuys,
I'm working through this same situation. I am about 90% there, but still a little foggy on this process. I can get a design to boot from flash by setting the reset vector to flash. I do have a few more questions though. 1. Does the nios ii exception vector point to on chip memory or also point to flash? 2. Am I correct in setting my hal.linker section in the bsp editor to the sdram controller? Below is a screenshot of my settings https://www.alteraforum.com/forum/attachment.php?attachmentid=9831 3. Under the linker script tab do I set all of the sections to sdram or just .heap and .stack? Below is another screen shot of the settings I'm talking about. https://www.alteraforum.com/forum/attachment.php?attachmentid=9832 For some reason I still can't get my c-code running with this configuration. Anything obvious I'm missing?
