Required Nios components

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Burst transfers shouldn't make a big difference on an SRAM. As for the cache line size, as dsl says the size is in bytes and not bits. Each time a transfer is required between the cache and the main memory, a full line will be read/written. Whether 16 or 32 is better depends a lot on the application (both hardware and software). You can try both and see if one performs better than the other on your system.

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Thanks for explaining this. My present application involves storing and retrieving 16-bit audio samples, so this will be an important consideration.

If you are only storing 16bit audio in the external memory, and are not accessing them sequentially (at least in the critical paths) it might be worth using uncached accesses and a 16bit slave (zero or sign extended to taste!)

There is also nothing (in principle at least) accessing the physical memory from two different avalon slaves (at different addresses), one giving 16bit accesses, the other 32bit (by doing two physical accesses).

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I have replaced the DDR2 memory with on-chip memory (262144 bytes), but the issue somehow was 125MHz clock. I have set the 50MHz clock instead and the Nios started.

The 125MHz clock was running for sure, I have made a blinker which works either with 125MHz clock or with 50MHz clock.

The development board is Cyclone III Host board from Altera (2 clocks on board + SMA IN)

Now the strange problem is that the console doesn't show anything. It runs the CPU:

I've checked BSP parameters, the stdin/stdout/stderr are all set to uart_jtag, but the console screen is empty.

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I know this was quite a while ago, Socrates, but I'm having this same problem now. I'm wondering if you were able to solve this issue of no output on the Nios Console.

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Yes. Connect all the system peripherals through pipeline bridge (e.g. sysid, jtag, timers, etc). Also fix timing warnings. It is possible to run Nios II @ 133MHz on Cyclone speed grade 8 and ~160MHz on the fastest speed grade. Maybe more, but I've not tested that.

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Thanks for the suggestion Socrates. I am really hopefull that this will get me out of the rut that I have been in for the past several days. However, now I am back to the old problem that keeps showing up whereby the System ID and Timestamp cannot be found.

The system is running at a conservative 50 MHz and Timequest is not complaining about not meeting constraints.

I tried with the Sys_ID component inside and outside the pipeline bridge, but neither work. It was working before I added the pipeline bridge to the Qsys design.

I attached a screen shot of my Qsys design as it stands now.

Great suggestion Socrates. I found an issue with the reset circuitry on my custom board - it was in desperate need of a pull-up resistor! That solved my problem.

Thanks for the help.