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Altera_Forum
Honored Contributor
Honored ContributorRequired Nios components
Hello, I am trying to develop a very simple Nios cpu to run Hello world application. I have created a design: http://i55.tinypic.com/a29isy.jpg As You can see, I have inserted DDR2 memory ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Burst transfers shouldn't make a big difference on an SRAM. As for the cache line size, as dsl says the size is in bytes and not bits. Each time a transfer is required between the cache and the main memory, a full line will be read/written. Whether 16 or 32 is better depends a lot on the application (both hardware and software). You can try both and see if one performs better than the other on your system. --- Quote End --- Thanks for explaining this. My present application involves storing and retrieving 16-bit audio samples, so this will be an important consideration.
