Forum Discussion
Honored ContributorRequired Nios components
Hello,
I am trying to develop a very simple Nios cpu to run Hello world application. I have created a design: http://i55.tinypic.com/a29isy.jpg As You can see, I have inserted DDR2 memory to store required code. The whole system should run from altmemddr PLL. However, the EDS tool doesn't find neither sysid, nor timestamp. What is wrong with this design? I have tried to add timer, but that didn't help and afaik it is not required. DDR2 pins are OK, I have taken them from a working example from development board CD.47 Replies
Altera_ForumAre the byte enable signals correctly connected to your 16-bits SRAM? Looking at your text again, it seem that on each 16-bit word is in fact the second byte repeated twice (I don't know if it is very clear, expressed like that). It could be that when the CPU is trying to do a 8-bit write to memory using byte enables, the memory write the same byte twice instead.
It should be possible to test 8-bit writes using custom HDL or the system console tools.- Altera_Forum
Remember the nios will always do 32bit reads (with all 4 byte enables driven).
- Altera_Forum
....im scared about it........
which board you are using?????? - Altera_Forum
I can't actually imagine that the cpu would run well enough to execute the memory test code at all if the memory was generating errors like those shown.
Possibly that is some artifact of the JTAG uart interface itself, it ought to run happily at 50MHz without any pipeline bridges at all. - Altera_Forum
You need to constrain tck to run at at least 10MHz if you're using timequest (20MHz if you use the old timing analyser). The On-board USB-Blaster in the neek runs tck at upto 8MHz.
Also, there is probably little benefit to running the Avalon clock for the JTAG UART so slowly - I would run that at 20MHz or more (and check it meets timing) - Altera_Forum--- Quote Start --- I can't actually imagine that the cpu would run well enough to execute the memory test code at all if the memory was generating errors like those shown. --- Quote End --- The CPU only uses 32-bit reads to load the code, doesn't it? If there were a problem with byte enables as I suggested, it would mostly show up during I/O, but probably not before...
- Altera_Forum
Here's another clue as to what might be happening...
When I program this: int main() { printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz \n"); printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz \n"); printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz \n"); printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz \n"); printf("Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz \n"); return 0; } I get this: Hello from Nios II! 1234567890abcdefghijklmnopqrttvvxxzz eell rrmmNNoo II 2244668800bbddffhhjjllnnpprrttvvxxzz Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz eell rrmmNNoo II 2244668800bbddffhhjjllnnpprrttvvxxzz eell rrom Nios II! 1234567890abcdefghijklmnopqrstuvwxyz eell rrmmNNoo II 2244668800bbddffhhjjllnnpprrttvvxxzz Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz eell rrmmNNoo II 2244668800bbddffhhjjllnnpprrttvvxxzz Hello from Nios II! 1234567890abcdefghijklmnopqrstuvwxyz eell rrmmNNoo II 2244668800bbddffhhjjllnnpprrttvvxxzz Hello from Nios II! 1234567890abcdefghijklmnpprrttvvxxzz eell rrmmNNoo II 2244668800bbddffhhjjllnnpprrttvvxxzz - Altera_Forum
I checked the signals on the JTAG port on my custom board. TCK is running around 6 MHz with the JTAG UART in Qsys running at 100 MHz. The Nios II CPU along with everything else in Qsys is also running at 100 MHz. No problems except this Nios II Console stuff.
- Altera_Forum
Is the system running from on chip memory or external memory?
- Altera_Forum
The Nios II software is running from external 516K x 16 SRAM.
I have an on-chip RAM block running as tightly coupled instruction memory in which I have configured the Nios II CPU to use for he reset and exception vectors.
