remote update module for cyclone 10 GX
I’m working with a Cyclone 10 GX FPGA with Quartus Prime 23.4.0 Build 79 11/22/2023 SC Pro Edition and the Ashling IDE v23.4.1, 3rd Nov 2023
using the remote update module to switch between factory and application images stored in a configuration device (MT25QU512). When generating a .jic file containing both factory and application images, the FPGA reconfiguration process from factory mode to application mode fails if I reduce the DCLK divisor from /32 to /2 (increasing DCLK to 25 MHz). With the original /32 divisor, reconfiguration works, but the configuration time is about 3 minutes. The flash memory supports DCLK frequencies up to 90 MHz, and the watchdog timer is set to its maximum value (0xFFF). The FPGA works correctly when the .jic file contains only one image (either factory or application).
The issue seems to be related to timing during the reconfiguration process at higher DCLK frequencies. Has anyone encountered similar issues or have insights on resolving this?