Forum Discussion
Hi,
- I assume you have follow the remote update IP userguide? https://www.intel.com/content/www/us/en/docs/programmable/683695/19-4-19-1-0/and-devices.html
- Can you provide us the scopeshot for before and after the clk speed is increase?
Regards,
Aiman
- Paul361 year ago
New Contributor
Hi Aiman,
Sorry for the late response as my company block this page and i try to use another account to reply.
Regarding the DCLK on the configuration device: before increasing the clock speed, the default setting of the clock divisor is 0x10 (which corresponds to a division by 32), resulting in a DCLK frequency of 1.5625 MHz. After changing the divisor to 0x1 (which corresponds to a division by 2), the DCLK frequency increased to 25 MHz, given that the input clock to the generic serial flash module is 50 MHz. This output appears to be as expected.
As for my understanding of the remote update module:
In the application image code, we can set the timeout value by writing to the RU_WATCHDOG_TIMEOUT parameter. Afterward, we enable the watchdog by setting the RU_WATCHDOG_ENABLE parameter to 1. To prevent the system from reconfiguring to the factory image, we need to periodically reset the timer by writing a value to RU_RESET_TIMER.
However, it seems that the watchdog does not function as intended, even though it is enabled and the timer is not being reset. Could you help me verify if I have misunderstood any of these functions?
Thanks
Paul