Reduce Interrupt latency?

There are many techniques to improve your interrupt response time. Add your own custom instruction to save/restore registers is one possibility but there may be other approaches that are easier.

If you have any spare on-chip memories, you can add a tightly-coupled instruction memory and tightly-coupled data memory. The Altera HAL supports a separate exception stack that you can place in the tightly-coupled data memory. Also, you can arrange to have the Altera HAL exception handler and your ISR linked to run in the tightly-coupled instruction memory. This way when an interrupt occurs, there are no cache misses in the exception handler code or for the data accesses it makes to save/restore registers.

I believe documentation for this approach is available and there are software and hardware examples.

Thanks James for giving me a reply

But i already used tightly coupled memory and on-chip memory.also put interrupt priority for usb at highest level..I did all the thing that mentioned in chapter 6 of nios software manual.I also made some custome instruction.

But if u have a idea about how to access NIOS register using custome instruction then let me know ASAP..ok

Best Regards,

SLS

I've uploaded a custom instruction I developed to reduce interrupt latency.

It is located in the "Post your own IP" section of this forum.

The custom instruction replaces a bunch of assembly instructions in the HAL/MicroC/OS-II exception handler that calls your ISR.

How about you give this a try and see if it meets your needs?

You can always use it in conjunction with your own custom instruction to save/restore registers if you need to.

Hi james

Thanx for ur reply

I downloaded ur custome instruction and as u suggest i did that thing.

Add in sopc and build again.

Ur custome instruction contain perl script and class.ptf.

Also i get the entry of ALT_CI_EXCEPTION_VECTOR 0x00000000 in system.h file but how to use this instruction in software and where?

If possible then can u give me some detail working of ur custome instruction..I already used tightly coupled memory.

when i ran the code i will not get any timing change in ISR..So is there any specific way to use ur custome instrucion?PLZ reply me SOON..waiting for ur reply.

Best Regards,

slsnios

Hey anybody can help me on this??

If possible then let me know....I am waiting for some solution or just give me an idea about how to access the register bank of nios II cpu directly using custome instruction.

PL:for detail just read above conversation...

Best Regards,

slsnios

The Altera HAL is already setup to use this custom instruction if present (assuming you are using Nios II 5.0 or later).

Look for# ifdef ALT_CI_EXCEPTION_VECTOR in components/altera_hal/HAL/src/alt_irq_handler.c and# ifdef ALT_CI_EXCEPTION_VECTOR_N in components/altera_nios2/HAL/src/alt_irq_entry.S. These component directories are under your Nios II kit (e.g. c:\altera\kits\nios2\component).

You might want to look at your objdump and make sure your ELF contains the custom instructions in the HAL exception handler code (should show up twice in your ELF). To generate an objdump that only shows the assembly instructions present in your ELF (and doesn't mix in the C source), use:

nios2-elf-objdump -sdtx *.elf >*.txt

BTW, your system.h should look like this when the custom instruction is present:

/*

* custom instruction macros

*

*/

# define ALT_CI_EXCEPTION_VECTOR_N 0x00000000# define ALT_CI_EXCEPTION_VECTOR __builtin_custom_in(ALT_CI_EXCEPTION_VECTOR_N)

The custom instruction returns a negative value when there are no interrupts pending. Otherwise, it returns the value of the highest priority interrupt (0 is highest priority) multipled by 8 (to properly index into the HAL ISR table).

FYI, am running with new CI sucessfully.

I don't know what the latency was because I couldn't get it to fit in my SignalTap buffer, but its only 160-180 clocks now. (yeah !!!)

I'm running 100MHz so that's like 1.6 usec.

Thanks much!

Now, can you tell me why my DMA's to sdram are usually about 1 clock per xfer, but sometimes they are *exactly* 16 clocks per xfer?

BTW, love the tightly coupled mems. I'm using it for data only. Looking fwd to the C2H as well.

Ken