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Altera_Forum's avatar
Altera_Forum
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20 years ago

Reduce Interrupt latency?

Hi I am working on NIOS fast cpu at 100Mhz and my problmae is that i am laging in timing issues at the time of Interrupt come from the device. I am developing HAL for USB device and when device...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

FYI, am running with new CI sucessfully.

I don't know what the latency was because I couldn't get it to fit in my SignalTap buffer, but its only 160-180 clocks now. (yeah !!!)

I'm running 100MHz so that's like 1.6 usec.

Thanks much!

Now, can you tell me why my DMA's to sdram are usually about 1 clock per xfer, but sometimes they are *exactly* 16 clocks per xfer?

BTW, love the tightly coupled mems. I'm using it for data only. Looking fwd to the C2H as well.

Ken