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Balerion's avatar
Balerion
Icon for Occasional Contributor rankOccasional Contributor
9 months ago
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Nios-V alt_epcq_controller_write() Problem

Hi, I have a flash on my custom board which is MT25QU01G. The flash is connected to Nios-V/g with Epcq Controller. I am trying to erase, write, read sectors from flash. Before write and erase I unlo...
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Nios Architecture
Nios Cpu
  • ShoH_Altera's avatar
    ShoH_Altera
    9 months ago

    Hi Balerion,

    Regading to avl_mem slave:

    If you also place avl_mem slave in Peripheral Region, you can use the current altera_epcq_controller.c file as is.

    However, you may want to place avl_mem slave in cacheable (non-Peripheral) region to take advantage of the cache for read accesses.  In that case, cache maintenance needed for flash memory write operation in Nios V/g system.  Here is a code example (= not fully validated) to achieve this attached (please replace the file extension from ".txt" to ".c").   At the end of the alt_epcq_controller_write_block() function, cache flush function call and error checking are added.

    Thanks,
    ShoH

ShoH_Altera's avatar
ShoH_Altera
Icon for Occasional Contributor rankOccasional Contributor
9 months ago

I see that you are using Serial Flash Controller.
Cached and non-cached regions( = peripheral regions) are specified in your HW design (Nios V IP configuration in PlatformDesigner).   If the HW design was not designed by you, please check with your HW designer.  (I think UART or JTAG-UART is used in your design and the UART works as expected.  If so, the UART registers should already be correctly located in a peripheral region. )
https://www.intel.com/content/www/us/en/docs/programmable/726952/25-1/memory-configurations-tab.html

Regards,
Sho

Balerion's avatar
Balerion
Icon for Occasional Contributor rankOccasional Contributor
9 months ago

Hi,

I looked at memory configuration page and see that my Data cache and Instruction cache sizes are 4KiloBytes. All my Peripheral regions and Tightly coupled memory settings are 0. My jtag uart base address is 0x48050060. I am able to use jtag uart without a problem. Is there anything you want me to check?

Thanks,

Balerion

  • ShoH_Altera's avatar
    ShoH_Altera
    Icon for Occasional Contributor rankOccasional Contributor
    9 months ago

    Hi Balerion,

    Thanks for checking.  OK, I need to say:  You must locate registers of peripheral IPs in a peripheral region.  
    https://www.intel.com/content/www/us/en/docs/programmable/726952/25-1/peripheral-region.html 
    If the jtag uart appears to work within your current system, please consider it a coincidence.

    At a minimum, in your system, you must define a Peripheral Region to place the jtag uart and the epcq avl_csr registers in peripheral region, such like:
      Peripheral Region Size : 64 KBytes or larger
      Peripheral Region Base Address : 0x48050000

    Thanks,
    Sho

    • Balerion's avatar
      Balerion
      Icon for Occasional Contributor rankOccasional Contributor
      9 months ago

      Hi ShoH,

      So, what I understand up to now is that there are two options for me. The first one is that I will disable caching in my nios-v/g configuration(0Kilobytes of cache) and the other option is that according to "https://www.intel.com/content/www/us/en/docs/programmable/726952/25-1/memory-configurations-tab.html" I have to place my peripherals to non-cached address space to do that I need to create peripheral region.

      There comes a few questions to my mind:

      • What differs between Peripheral A and Peripheral B and which one should I choose?
      • Let's say I create peripheral region, Do I need to also create tightly coupled memory region as well or peripheral region is enough?
      • Why do peripherals have to be located to the non-cached address space?

       

      Thanks,

      Balerion

       

      • ShoH_Altera's avatar
        ShoH_Altera
        Icon for Occasional Contributor rankOccasional Contributor
        9 months ago

        Hi Balerion,

        Yes, disable caching(0Kilobytes of cache) is another option and a good choice when you use Tightly Coupled Memories(TCMs).  (In my design, I usually disable cache when I can use sufficient size of TCMs.)

        • There is no difference between Peripheral A and Peripheral B for the core. You may use ether one.  When you feel convenient with two separeate peripheral region, you can use both.  These allow you to use separate regions for Peripheral.
        • Accessing TCM always bypasses cache memory(=Cache is never used for TCM accesses).  So you don't need to worry about peripheral region for TCM.
          https://www.intel.com/content/www/us/en/docs/programmable/683632/25-3/accessing-tightly-coupled-memory.html
        • "peripheral access must be non-cached" : Caches store copies of data, and accessing peripheral registers through a cache can result in reading "stale" data, or a write could be held in the cache and never write to the peripheral hardware.  Please note that this is due to the way CPU caches work and is not specific to Nios V.

        Please let me know if disabling cache or caring peripheral region helps to resolve the QSPI access issue.

        Thanks,
        ShoH