--- Quote Start --- This is jpe1313, What I was saying was that are any of your entries your generated *.dts file "unknown." Take a look. If they are "unknown" then it COULD be a problem. For my custom design my "timer" was undefined and I had to define it properly. As far as the SD card. To clarify, I am not using the SD card in my design. I have a daughter card that has a Compact Flash. Let me know if you need more help - but check your DTS --- Quote End --- I am not able to post without administrator's approval. So i sent my message here. I maybe wrote 5-6 times both topics but it seems all admins are sleeping. Please email me (occelebi at gmail) Because i can not send any message more than 1 Anyway, i have no unknown parameters. /* * This devicetree is generated by sopc2dts on Fri Apr 19 16:30:38 EEST 2013 * Sopc2dts is written by Walter Goossens <waltergoossens@home.nl> * in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw> */ /dts-v1/; / { model = "ALTR,onur"; compatible = "ALTR,onur"; # address-cells = < 1 >; # size-cells = < 1 >; cpus { # address-cells = < 1 >; # size-cells = < 0 >; cpu: cpu@0x0 { device_type = "cpu"; compatible = "ALTR,nios2-12.1"; reg = < 0x00000000 >; interrupt-controller; # interrupt-cells = < 1 >; clock-frequency = < 50000000 >; /* embeddedsw.CMacro.CPU_FREQ type NUMBER */ dcache-line-size = < 32 >; /* embeddedsw.CMacro.DCACHE_LINE_SIZE type NUMBER */ icache-line-size = < 32 >; /* embeddedsw.CMacro.ICACHE_LINE_SIZE type NUMBER */ dcache-size = < 2048 >; /* embeddedsw.CMacro.DCACHE_SIZE type NUMBER */ icache-size = < 4096 >; /* embeddedsw.CMacro.ICACHE_SIZE type NUMBER */ ALTR,implementation = "fast"; /* embeddedsw.CMacro.CPU_IMPLEMENTATION type STRING*/ ALTR,pid-num-bits = < 8 >; /* embeddedsw.CMacro.PROCESS_ID_NUM_BITS type NUMBER */ ALTR,tlb-num-ways = < 16 >; /* embeddedsw.CMacro.TLB_NUM_WAYS type NUMBER */ ALTR,tlb-num-entries = < 256 >; /* embeddedsw.CMacro.TLB_NUM_ENTRIES type NUMBER */ ALTR,tlb-ptr-sz = < 8 >; /* embeddedsw.CMacro.TLB_PTR_SZ type NUMBER */ ALTR,has-mul; /* embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT type NUMBER*/ ALTR,reset-addr = < 0xc0000000 >; /* embeddedsw.CMacro.RESET_ADDR type NUMBER */ ALTR,fast-tlb-miss-addr = < 0xc8001000 >; /* embeddedsw.CMacro.FAST_TLB_MISS_EXCEPTION_ADDR type NUMBER */ ALTR,exception-addr = < 0xc0000020 >; /* embeddedsw.CMacro.EXCEPTION_ADDR type NUMBER */ }; //end cpu@0x0 (cpu) }; //end cpus memory@0 { device_type = "memory"; reg = < 0x08001000 0x00000400 0x00000000 0x08000000 >; }; //end memory@0 sopc@0 { device_type = "soc"; ranges; # address-cells = < 1 >; # size-cells = < 1 >; compatible = "ALTR,avalon", "simple-bus"; bus-frequency = < 50000000 >; jtag: serial@0x8001440 { compatible = "ALTR,juart-12.1", "ALTR,juart-1.0"; reg = < 0x08001440 0x00000008 >; interrupt-parent = < &cpu >; interrupts = < 1 >; }; //end serial@0x8001440 (jtag) timer: timer@0x8001420 { compatible = "ALTR,timer-12.1", "ALTR,timer-1.0"; reg = < 0x08001420 0x00000020 >; interrupt-parent = < &cpu >; interrupts = < 0 >; clock-frequency = < 50000000 >; }; //end timer@0x8001420 (timer) }; //end sopc@0 chosen { bootargs = "debug console=ttyJ0,115200"; }; //end chosen }; //end / And i also made my friend compile my kernel and .sopc file and tried to new zImage but terminal gave me same output :/ root@F15:~# altera/12.1/nios2eds/bin/nios2-download -g /home/student/Downloads/zImage Using cable "USB-Blaster [8-1]", device 1, instance 0x00 Pausing target processor: not responding. Resetting and trying again: FAILED Leaving target processor paused I hope you can even help further. Regards, Cem

Hello, Usually if your processor can't be even reset the problem is your processor is not running. It will happen if you have no clock. Also, check your compilation report for critical warnings. Unassigned pins may cause this problem too. Check for timing issues. If you have a processor with the jtag-debug enabled and the processor is running then the processor should be successfully reset through the jtag debug interface by the nios2-download command.

--- Quote Start --- Hello, Usually if your processor can't be even reset the problem is your processor is not running. It will happen if you have no clock. Also, check your compilation report for critical warnings. Unassigned pins may cause this problem too. Check for timing issues. If you have a processor with the jtag-debug enabled and the processor is running then the processor should be successfully reset through the jtag debug interface by the nios2-download command. --- Quote End --- Thank you for your help. There are such a clock which i dont know where to assign them. So i paste here all critical errors. Critical Warning (332012): Synopsys Design Constraints File file not found: 'onur.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) Critical Warning (332012): Synopsys Design Constraints File file not found: 'onur.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) Or maybe you want to edit it yourself. In this case i've sent my files too.

I'm sorry, your .tar doesn't include all the files I need. Can you please create a project archive? From the "Project" menu, select "Archive Project". It will create a .qar file you can post here. Only the .qsys will be missing, but you've sent that already.

Sure, i can. You can find that in attachment. Thanks in advance.

Please check the switches on your board. You have your reset signal set to SW17. Your design seems to be working. I can only reproduce your error when I set SW17 to OFF (closer to the board edge).

Forum Discussion

Altera_Forum

Honored Contributor

12 years ago

Problem when downloading zImage to DE2-115 (cont.)

--- Quote Start ---

This is jpe1313,

What I was saying was that are any of your entries your generated *.dts file "unknown." Take a look. If they are "unknown" then it COULD be a problem. For my custom design my "timer" was undefined and I had to define it properly. As far as the SD card. To clarify, I am not using the SD card in my design. I have a daughter card that has a Compact Flash.

Let me know if you need more help - but check your DTS

--- Quote End ---

I am not able to post without administrator's approval. So i sent my message here. I maybe wrote 5-6 times both topics but it seems all admins are sleeping. Please email me (occelebi at gmail) Because i can not send any message more than 1

Anyway, i have no unknown parameters.

* This devicetree is generated by sopc2dts on Fri Apr 19 16:30:38 EEST 2013

* Sopc2dts is written by Walter Goossens <waltergoossens@home.nl>

* in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw>

/dts-v1/;

/ {

model = "ALTR,onur";

compatible = "ALTR,onur";

# address-cells = < 1 >;

# size-cells = < 1 >;

cpus {

# address-cells = < 1 >;

# size-cells = < 0 >;

cpu: cpu@0x0 {

device_type = "cpu";

compatible = "ALTR,nios2-12.1";

reg = < 0x00000000 >;

interrupt-controller;

# interrupt-cells = < 1 >;

clock-frequency = < 50000000 >; /* embeddedsw.CMacro.CPU_FREQ type NUMBER */

dcache-line-size = < 32 >; /* embeddedsw.CMacro.DCACHE_LINE_SIZE type NUMBER */

icache-line-size = < 32 >; /* embeddedsw.CMacro.ICACHE_LINE_SIZE type NUMBER */

dcache-size = < 2048 >; /* embeddedsw.CMacro.DCACHE_SIZE type NUMBER */

icache-size = < 4096 >; /* embeddedsw.CMacro.ICACHE_SIZE type NUMBER */

ALTR,implementation = "fast"; /* embeddedsw.CMacro.CPU_IMPLEMENTATION type STRING*/

ALTR,pid-num-bits = < 8 >; /* embeddedsw.CMacro.PROCESS_ID_NUM_BITS type NUMBER */

ALTR,tlb-num-ways = < 16 >; /* embeddedsw.CMacro.TLB_NUM_WAYS type NUMBER */

ALTR,tlb-num-entries = < 256 >; /* embeddedsw.CMacro.TLB_NUM_ENTRIES type NUMBER */

ALTR,tlb-ptr-sz = < 8 >; /* embeddedsw.CMacro.TLB_PTR_SZ type NUMBER */

ALTR,has-mul; /* embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT type NUMBER*/

ALTR,reset-addr = < 0xc0000000 >; /* embeddedsw.CMacro.RESET_ADDR type NUMBER */

ALTR,fast-tlb-miss-addr = < 0xc8001000 >; /* embeddedsw.CMacro.FAST_TLB_MISS_EXCEPTION_ADDR type NUMBER */

ALTR,exception-addr = < 0xc0000020 >; /* embeddedsw.CMacro.EXCEPTION_ADDR type NUMBER */

}; //end cpu@0x0 (cpu)

}; //end cpus

memory@0 {

device_type = "memory";

reg = < 0x08001000 0x00000400

0x00000000 0x08000000 >;

}; //end memory@0

sopc@0 {

device_type = "soc";

ranges;

# address-cells = < 1 >;

# size-cells = < 1 >;

compatible = "ALTR,avalon", "simple-bus";

bus-frequency = < 50000000 >;

jtag: serial@0x8001440 {

compatible = "ALTR,juart-12.1", "ALTR,juart-1.0";

reg = < 0x08001440 0x00000008 >;

interrupt-parent = < &cpu >;

interrupts = < 1 >;

}; //end serial@0x8001440 (jtag)

timer: timer@0x8001420 {

compatible = "ALTR,timer-12.1", "ALTR,timer-1.0";

reg = < 0x08001420 0x00000020 >;

interrupt-parent = < &cpu >;

interrupts = < 0 >;

clock-frequency = < 50000000 >;

}; //end timer@0x8001420 (timer)

}; //end sopc@0

chosen {

bootargs = "debug console=ttyJ0,115200";

}; //end chosen

}; //end /

And i also made my friend compile my kernel and .sopc file and tried to new zImage but terminal gave me same output :/

root@F15:~# altera/12.1/nios2eds/bin/nios2-download -g /home/student/Downloads/zImage

Using cable "USB-Blaster [8-1]", device 1, instance 0x00

Pausing target processor: not responding.

Resetting and trying again: FAILED

Leaving target processor paused

I hope you can even help further.

Regards,

Cem

19 Replies

Altera_Forum
Honored Contributor
12 years ago
Hello,

Usually if your processor can't be even reset the problem is your processor is not running. It will happen if you have no clock. Also, check your compilation report for critical warnings. Unassigned pins may cause this problem too. Check for timing issues. If you have a processor with the jtag-debug enabled and the processor is running then the processor should be successfully reset through the jtag debug interface by the nios2-download command.
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
Hello,

Usually if your processor can't be even reset the problem is your processor is not running. It will happen if you have no clock. Also, check your compilation report for critical warnings. Unassigned pins may cause this problem too. Check for timing issues. If you have a processor with the jtag-debug enabled and the processor is running then the processor should be successfully reset through the jtag debug interface by the nios2-download command.
--- Quote End ---

Thank you for your help. There are such a clock which i dont know where to assign them. So i paste here all critical errors.

Critical Warning (332012): Synopsys Design Constraints File file not found: 'onur.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)
Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)
Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)
Critical Warning (332012): Synopsys Design Constraints File file not found: 'onur.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)
Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)
Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)
Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)
Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)
Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)
Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)

Or maybe you want to edit it yourself. In this case i've sent my files too.
quartus1.tar240 KB
Altera_Forum
Honored Contributor
12 years ago
I'm sorry, your .tar doesn't include all the files I need. Can you please create a project archive?

From the "Project" menu, select "Archive Project". It will create a .qar file you can post here. Only the .qsys will be missing, but you've sent that already.
Altera_Forum
Honored Contributor
12 years ago
Sure, i can. You can find that in attachment. Thanks in advance.
onur.qar643 KB
Altera_Forum
Honored Contributor
12 years ago
Please check the switches on your board. You have your reset signal set to SW17.

Your design seems to be working. I can only reproduce your error when I set SW17 to OFF (closer to the board edge).
Altera_Forum
Honored Contributor
12 years ago
I set SW 17 to ON (UP) and tried it again, but it did not work. Same error appeared again.

Did you generate a new zImage ? Maybe something is missing on that part.

Altera_Forum

Honored Contributor

12 years ago

The error you are getting is not related to your zImage. The process of resetting the processor should work with any image, even a nios2-elf (though it would fail afterwards).

I'm attaching the sof I compiled from your project, try and see if it works for you, it is the one which is working here.

Unfortunatelly I can't send you the zImage, but it must work with yours. If not, I'd advice you to check your board (with other designs, maybe the board test system).

Here is the command I used and its output.


~/Downloads/onur_restored$ nios2-configure-sof output_files/onur.sof && nios2-download -g ~/nios2-linux/uClinux-dist/images/zImage
Info: *******************************************************************
Info: Running Quartus II 64-Bit Programmer
Info: Command: quartus_pgm --no_banner --mode=jtag -o p;./output_files/onur.sof
Info (213045): Using programming cable "USB-Blaster "
Info (213011): Using programming file ./output_files/onur.sof with checksum 0x008EA0A1 for device EP4CE115F29@1
Info (209060): Started Programmer operation at Mon May  6 09:39:28 2013
Info (209016): Configuring device index 1
Info (209017): Device 1 contains JTAG ID code 0x020F70DD
Info (209007): Configuration succeeded -- 1 device(s) configured
Info (209011): Successfully performed operation(s)
Info (209061): Ended Programmer operation at Mon May  6 09:39:34 2013
Info: Quartus II 64-Bit Programmer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 281 megabytes
    Info: Processing ended: Mon May  6 09:39:34 2013
    Info: Elapsed time: 00:00:07
    Info: Total CPU time (on all processors): 00:00:01
Using cable "USB-Blaster ", device 1, instance 0x00
Pausing target processor: OK
Initializing CPU cache (if present)
OK
Downloading D13E0000 (76%)

onur.sof.zip152 KB

Altera_Forum
Honored Contributor
12 years ago
Thank you, finally it works !

root@F15:~# altera/12.1/nios2eds/bin/nios2-download -g /home/student/luclinux/uClinux-dist/linux-2.6.x/arch/nios2/boot/zImage
Using cable "USB-Blaster [8-1]", device 1, instance 0x00
Pausing target processor: OK
Initializing CPU cache (if present)
OK
Downloaded 1421KB in 28.6s (49.6KB/s)
Verifying C1000000 ( 0%)
Verify failed between address 0xC1000000 and 0xC100FFFF
Leaving target processor paused

And i also wonder that how to make it work ?

But now i am stucked on nios2-terminal.

root@F15:~/altera/12.1/nios2eds/bin#./nios2-terminal

nios2-terminal: connected to hardware target using JTAG UART on cable
nios2-terminal: "USB-Blaster [8-1]", device 1, instance 0
nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)

It stucks on there.
Altera_Forum
Honored Contributor
12 years ago
You got "Verify failed". It means the image was not correctly written to your memory device at address 0X01000000 + 0xC0000000 (offset added by MMU)

If you are using the same .qsys you sent me there's no memory at this address. It means your kernel is misconfigured. You must set your memory base address in the kernel configuration menu. Also, your memory must be working fine, otherwise you'll get the same error.

Good luck!
Altera_Forum
Honored Contributor
12 years ago
I ignored the message you pointed out due to happiness of success.

Ok lets examine kernel configuration. Memory base address is set to 0x0 and Link address offset is set to 0x0100_0000.

As you know SDRAM starts at 0x0000_0000 in my .qsys file. So how to configure kernel to get it work ?

Forum Discussion

Problem when downloading zImage to DE2-115 (cont.)

19 Replies

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