--- Quote Start --- This is jpe1313, What I was saying was that are any of your entries your generated *.dts file "unknown." Take a look. If they are "unknown" then it COULD be a problem. For my custom design my "timer" was undefined and I had to define it properly. As far as the SD card. To clarify, I am not using the SD card in my design. I have a daughter card that has a Compact Flash. Let me know if you need more help - but check your DTS --- Quote End --- I am not able to post without administrator's approval. So i sent my message here. I maybe wrote 5-6 times both topics but it seems all admins are sleeping. Please email me (occelebi at gmail) Because i can not send any message more than 1 Anyway, i have no unknown parameters. /* * This devicetree is generated by sopc2dts on Fri Apr 19 16:30:38 EEST 2013 * Sopc2dts is written by Walter Goossens <waltergoossens@home.nl> * in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw> */ /dts-v1/; / { model = "ALTR,onur"; compatible = "ALTR,onur"; # address-cells = < 1 >; # size-cells = < 1 >; cpus { # address-cells = < 1 >; # size-cells = < 0 >; cpu: cpu@0x0 { device_type = "cpu"; compatible = "ALTR,nios2-12.1"; reg = < 0x00000000 >; interrupt-controller; # interrupt-cells = < 1 >; clock-frequency = < 50000000 >; /* embeddedsw.CMacro.CPU_FREQ type NUMBER */ dcache-line-size = < 32 >; /* embeddedsw.CMacro.DCACHE_LINE_SIZE type NUMBER */ icache-line-size = < 32 >; /* embeddedsw.CMacro.ICACHE_LINE_SIZE type NUMBER */ dcache-size = < 2048 >; /* embeddedsw.CMacro.DCACHE_SIZE type NUMBER */ icache-size = < 4096 >; /* embeddedsw.CMacro.ICACHE_SIZE type NUMBER */ ALTR,implementation = "fast"; /* embeddedsw.CMacro.CPU_IMPLEMENTATION type STRING*/ ALTR,pid-num-bits = < 8 >; /* embeddedsw.CMacro.PROCESS_ID_NUM_BITS type NUMBER */ ALTR,tlb-num-ways = < 16 >; /* embeddedsw.CMacro.TLB_NUM_WAYS type NUMBER */ ALTR,tlb-num-entries = < 256 >; /* embeddedsw.CMacro.TLB_NUM_ENTRIES type NUMBER */ ALTR,tlb-ptr-sz = < 8 >; /* embeddedsw.CMacro.TLB_PTR_SZ type NUMBER */ ALTR,has-mul; /* embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT type NUMBER*/ ALTR,reset-addr = < 0xc0000000 >; /* embeddedsw.CMacro.RESET_ADDR type NUMBER */ ALTR,fast-tlb-miss-addr = < 0xc8001000 >; /* embeddedsw.CMacro.FAST_TLB_MISS_EXCEPTION_ADDR type NUMBER */ ALTR,exception-addr = < 0xc0000020 >; /* embeddedsw.CMacro.EXCEPTION_ADDR type NUMBER */ }; //end cpu@0x0 (cpu) }; //end cpus memory@0 { device_type = "memory"; reg = < 0x08001000 0x00000400 0x00000000 0x08000000 >; }; //end memory@0 sopc@0 { device_type = "soc"; ranges; # address-cells = < 1 >; # size-cells = < 1 >; compatible = "ALTR,avalon", "simple-bus"; bus-frequency = < 50000000 >; jtag: serial@0x8001440 { compatible = "ALTR,juart-12.1", "ALTR,juart-1.0"; reg = < 0x08001440 0x00000008 >; interrupt-parent = < &cpu >; interrupts = < 1 >; }; //end serial@0x8001440 (jtag) timer: timer@0x8001420 { compatible = "ALTR,timer-12.1", "ALTR,timer-1.0"; reg = < 0x08001420 0x00000020 >; interrupt-parent = < &cpu >; interrupts = < 0 >; clock-frequency = < 50000000 >; }; //end timer@0x8001420 (timer) }; //end sopc@0 chosen { bootargs = "debug console=ttyJ0,115200"; }; //end chosen }; //end / And i also made my friend compile my kernel and .sopc file and tried to new zImage but terminal gave me same output :/ root@F15:~# altera/12.1/nios2eds/bin/nios2-download -g /home/student/Downloads/zImage Using cable "USB-Blaster [8-1]", device 1, instance 0x00 Pausing target processor: not responding. Resetting and trying again: FAILED Leaving target processor paused I hope you can even help further. Regards, Cem

Hello, Usually if your processor can't be even reset the problem is your processor is not running. It will happen if you have no clock. Also, check your compilation report for critical warnings. Unassigned pins may cause this problem too. Check for timing issues. If you have a processor with the jtag-debug enabled and the processor is running then the processor should be successfully reset through the jtag debug interface by the nios2-download command.

--- Quote Start --- Hello, Usually if your processor can't be even reset the problem is your processor is not running. It will happen if you have no clock. Also, check your compilation report for critical warnings. Unassigned pins may cause this problem too. Check for timing issues. If you have a processor with the jtag-debug enabled and the processor is running then the processor should be successfully reset through the jtag debug interface by the nios2-download command. --- Quote End --- Thank you for your help. There are such a clock which i dont know where to assign them. So i paste here all critical errors. Critical Warning (332012): Synopsys Design Constraints File file not found: 'onur.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) Critical Warning (332012): Synopsys Design Constraints File file not found: 'onur.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) Or maybe you want to edit it yourself. In this case i've sent my files too.

I'm sorry, your .tar doesn't include all the files I need. Can you please create a project archive? From the "Project" menu, select "Archive Project". It will create a .qar file you can post here. Only the .qsys will be missing, but you've sent that already.

Sure, i can. You can find that in attachment. Thanks in advance.

Please check the switches on your board. You have your reset signal set to SW17. Your design seems to be working. I can only reproduce your error when I set SW17 to OFF (closer to the board edge).

Forum Discussion

Altera_Forum

Honored Contributor

12 years ago

Problem when downloading zImage to DE2-115 (cont.)

--- Quote Start ---

This is jpe1313,

What I was saying was that are any of your entries your generated *.dts file "unknown." Take a look. If they are "unknown" then it COULD be a problem. For my custom design my "timer" was undefined and I had to define it properly. As far as the SD card. To clarify, I am not using the SD card in my design. I have a daughter card that has a Compact Flash.

Let me know if you need more help - but check your DTS

--- Quote End ---

I am not able to post without administrator's approval. So i sent my message here. I maybe wrote 5-6 times both topics but it seems all admins are sleeping. Please email me (occelebi at gmail) Because i can not send any message more than 1

Anyway, i have no unknown parameters.

* This devicetree is generated by sopc2dts on Fri Apr 19 16:30:38 EEST 2013

* Sopc2dts is written by Walter Goossens <waltergoossens@home.nl>

* in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw>

/dts-v1/;

/ {

model = "ALTR,onur";

compatible = "ALTR,onur";

# address-cells = < 1 >;

# size-cells = < 1 >;

cpus {

# address-cells = < 1 >;

# size-cells = < 0 >;

cpu: cpu@0x0 {

device_type = "cpu";

compatible = "ALTR,nios2-12.1";

reg = < 0x00000000 >;

interrupt-controller;

# interrupt-cells = < 1 >;

clock-frequency = < 50000000 >; /* embeddedsw.CMacro.CPU_FREQ type NUMBER */

dcache-line-size = < 32 >; /* embeddedsw.CMacro.DCACHE_LINE_SIZE type NUMBER */

icache-line-size = < 32 >; /* embeddedsw.CMacro.ICACHE_LINE_SIZE type NUMBER */

dcache-size = < 2048 >; /* embeddedsw.CMacro.DCACHE_SIZE type NUMBER */

icache-size = < 4096 >; /* embeddedsw.CMacro.ICACHE_SIZE type NUMBER */

ALTR,implementation = "fast"; /* embeddedsw.CMacro.CPU_IMPLEMENTATION type STRING*/

ALTR,pid-num-bits = < 8 >; /* embeddedsw.CMacro.PROCESS_ID_NUM_BITS type NUMBER */

ALTR,tlb-num-ways = < 16 >; /* embeddedsw.CMacro.TLB_NUM_WAYS type NUMBER */

ALTR,tlb-num-entries = < 256 >; /* embeddedsw.CMacro.TLB_NUM_ENTRIES type NUMBER */

ALTR,tlb-ptr-sz = < 8 >; /* embeddedsw.CMacro.TLB_PTR_SZ type NUMBER */

ALTR,has-mul; /* embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT type NUMBER*/

ALTR,reset-addr = < 0xc0000000 >; /* embeddedsw.CMacro.RESET_ADDR type NUMBER */

ALTR,fast-tlb-miss-addr = < 0xc8001000 >; /* embeddedsw.CMacro.FAST_TLB_MISS_EXCEPTION_ADDR type NUMBER */

ALTR,exception-addr = < 0xc0000020 >; /* embeddedsw.CMacro.EXCEPTION_ADDR type NUMBER */

}; //end cpu@0x0 (cpu)

}; //end cpus

memory@0 {

device_type = "memory";

reg = < 0x08001000 0x00000400

0x00000000 0x08000000 >;

}; //end memory@0

sopc@0 {

device_type = "soc";

ranges;

# address-cells = < 1 >;

# size-cells = < 1 >;

compatible = "ALTR,avalon", "simple-bus";

bus-frequency = < 50000000 >;

jtag: serial@0x8001440 {

compatible = "ALTR,juart-12.1", "ALTR,juart-1.0";

reg = < 0x08001440 0x00000008 >;

interrupt-parent = < &cpu >;

interrupts = < 1 >;

}; //end serial@0x8001440 (jtag)

timer: timer@0x8001420 {

compatible = "ALTR,timer-12.1", "ALTR,timer-1.0";

reg = < 0x08001420 0x00000020 >;

interrupt-parent = < &cpu >;

interrupts = < 0 >;

clock-frequency = < 50000000 >;

}; //end timer@0x8001420 (timer)

}; //end sopc@0

chosen {

bootargs = "debug console=ttyJ0,115200";

}; //end chosen

}; //end /

And i also made my friend compile my kernel and .sopc file and tried to new zImage but terminal gave me same output :/

root@F15:~# altera/12.1/nios2eds/bin/nios2-download -g /home/student/Downloads/zImage

Using cable "USB-Blaster [8-1]", device 1, instance 0x00

Pausing target processor: not responding.

Resetting and trying again: FAILED

Leaving target processor paused

I hope you can even help further.

Regards,

Cem

19 Replies

Altera_Forum
Honored Contributor
12 years ago
Yes, sorry, there's a SDRAM at 0x00000000 so it should be working. If it can't write to the memory and read the same content (verify) it means your memory is not working properly. Your design seems to be missing a clock to your SDRAM. You should add a PLL to generate a clock to your SDRAM. Please take a look at the projects found in the board CD-ROM (you can download it from Terasic site). You will find the right PLL configuration and other valuable information in these reference designs.
Altera_Forum
Honored Contributor
12 years ago
I've tried to design it with UP clocks that comes from Altera University program. But it did not work. Strange thing is that i can not even download zImage to board again. The error is the same as i had before.

Pausing target processor: not responding. Resetting and trying again: FAILED Leaving target processor paused

I also attached the design that produces that output.
files.tar910 KB
Altera_Forum
Honored Contributor
12 years ago
Sorry, I don't know what you mean by "UP clocks".

I've just added the PLL and connected the clock output to the DRAM_CLK pin PIN_AE5 (from DE2-115.qsf file available in Terasic site). The SDRAM is working now. There only difference from your project is the Qsys file and the pin assignment. The pin assignment is shown below and the new Qsys file is attached. I've successfully run uCLinux and though I can't sent you my zImage I guess yours should work too.

set_location_assignment PIN_AE5 -to DRAM_CLK

Please note that this design is far from good, it should at least have a SDC file. Though the design is now working, I want to make sure you understood what happened here so you can do it by yourself when you need.
onur.qsys.tar50 KB
Altera_Forum
Honored Contributor
12 years ago
I believe i did the work as you said. But even so it still did not work. I've attached files.

I started to believe my zImage may be somehow broken or make progress fails even it generates zImage in /uClinux-dist/linux-2.6.x/arch/nios2/boot directory.
new1.tar5 MB
Altera_Forum
Honored Contributor
12 years ago
It seems that i don't know how to compile from .qsys and generate .sof file. Because i am able compile and build these files and got .sof file. But it does not work. But your file which you've send me works smoothly. So, could you please explain me step by step what to do in compilation and build stage ?
Altera_Forum
Honored Contributor
12 years ago
Actually I did the following steps, you can try to do it and see what you get.

1. Open the project you posted, onur.qar
2. Copy Qsys project you posted, inside quartus1.tar, to the project directory, where onur.qpf is located
3. Edit your Qsys system in order to add a PLL. You can see the specs and connections I used or just use the Qsys I posted. You will export a pll output so your system will have an additional pin.
4. Generate your system. Make sure the path where the system will be generated is the same of the .qip file you added to your Quartus project.
5. Elaborate your project. Open the pin planner. Assign the newly created pin to PIN_AE5, which is the memory clock pin.
6. Compile your project.

I'm attaching my .sof with the working memory for you to make sure you zImage is working.
onur.sof.zip151 KB

Altera_Forum

Honored Contributor

12 years ago

Thank you. I managed to download and made it verify succesfully. But now it seems there is no filesystem to mount. Have you encountered that ?

root@F15:~/altera/12.1/nios2eds/bin# ./nios2-terminal
nios2-terminal: connected to hardware target using JTAG UART on cable
nios2-terminal: "USB-Blaster ", device 1, instance 0
nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)
Linux version 3.7.0-01377-g1061bd7-dirty (root@F15) (gcc version 4.1.2)# 16 Thu May 9 11:05:35 EEST 2013
bootconsole  enabled
early_console initialized at 0xe8001440
On node 0 totalpages: 32768
free_area_init_node: node 0, pgdat c02faac0, node_mem_map c0310780
  DMA zone: 256 pages used for memmap
  DMA zone: 0 pages reserved
  DMA zone: 32512 pages, LIFO batch:7
pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
pcpu-alloc:  0 
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 32512
Kernel command line: 
PID hash table entries: 512 (order: -1, 2048 bytes)
Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
Memory available: 126776k/3130k RAM (2387k kernel code, 742k data)
NR_IRQS:64
Calibrating delay loop... 23.45 BogoMIPS (lpj=46912)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
NET: Registered protocol family 16
bio: create slab <bio-0> at 0
Switching to clocksource timer
NET: Registered protocol family 2
TCP established hash table entries: 4096 (order: 3, 32768 bytes)
TCP bind hash table entries: 4096 (order: 2, 16384 bytes)
TCP: Hash tables configured (established 4096 bind 4096)
TCP: reno registered
UDP hash table entries: 256 (order: 0, 4096 bytes)
UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
msgmni has been set to 247
Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
ttyJ0 at MMIO 0x8001440 (irq = 1) is a Altera JTAG UART
console  enabled, bootconsole disabled
console  enabled, bootconsole disabled
mousedev: PS/2 mouse device common for all mice
TCP: cubic registered
NET: Registered protocol family 17
List of all partitions:
No filesystem could mount root, tried: 
Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)

Altera_Forum
Honored Contributor
12 years ago
I'm sorry, I've never had this problem. But I think I've seen it before on forums and all over the internet. I guess you'll find the answer easily.

I'm pretty sure you have something wrong in your kernel configuration, but I don't know how to help you here.
Altera_Forum
Honored Contributor
12 years ago
I got it work ! The problem about rootfs is that there is no rootfs that is called after kernel initialization. I included .cpio file into my kernel then problem disappeared.

Thanks, I really appreciated your contribution. New problem arised that I am able to compile the .sof file but after that i can not download my zImage in to the board. Weirdly, my design that compiled by you works smoothly. I tried to compile .sof file in my Windows machine too. But result remains same. Have you any idea about it ?

Forum Discussion

Problem when downloading zImage to DE2-115 (cont.)

19 Replies

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