Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorproblem of assign output pin
Hi,
i create an IP, and i add with sopc builder to my nios system. It work perfectly with the nios. The only problem is, i don't know how to assign the input/output signal of my IP which aren't connected to avalon bus and go directly outside. I put my signal in the conduit category, but after that i don't know how to assign them to the output/input pin of my fpga. Thank you6 Replies
Altera_ForumSelect Signal type = export in the sopc component editor.
Or directly with the add_interface_port instruction in tcl file: add_interface conduit_end conduit end add_interface_port conduit_end <your_ip_signal_name> export Output 1- Altera_Forum
yes, i have these lines. But after that how i assign these signals to a pin in the pin planner, there aren't show
- Altera_Forum
The same as all the other sopc block pins.
When you instantiate the sopc in the top level (HDL or schematic) you assign names to the wires connecting the sopc block I/Os to the top level I/Os (i.e. the fpga pins). If you never compiled the design you must manually insert this names in pin planner. If you compile once, then you'll find the pin names already there and you only need to assign them to the required location. - Altera_Forum
thank you, it appears now,
- Altera_Forum
where do you find the name of the port to assign in the top verilog lvl?
i doesn't arrive to compile. - Altera_Forum
I can't understand your question. :confused:
I thought you had already compiled the project. Maybe you mean you need this: File Menu -> Create/Update -> Create Verilog Instantiation Template for Current File
