Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

problem in building a new SOPC component

(originally put in software forum, but here is a better fit)

Hi,

I have a probelm in building a new SOPC component. I have this new

component, the PWM example, and a NIOSII cpu in the project. The

PWM works fine (using signalTap, I can see all the read/write control

signal changes). However, my new components does not work (with

signalTap, read/write control signal does not change. only address

change, but not the way I need).

Any idea what's going on will be appreciated?

Whether I need start a new slave_avalon bus? I think I using the right

address for my new module.

Thanks a lot,

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Building user peripheral for Nios processor is not easy job, I guess you knew this quite well.

    My suggestion will be:

    (1) make sure the Avalong bus interfacing is all right. (all standard bus signaling)

    (2) make sure your register file timing fits CPU's RD/WR operation.

    (3) Do ModelSim sim from IDE's hardware simulation. (Altera's AN351)

    Hope these will help,
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Hi:

    Could you please give some more details of your component? What kind of component is it? Is it an interface for some external chip, or just 'simple' logic?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Hi, VLorenzo and legendbb,

    My component start working. When using IORD/IOWR, I sent more bits than defined

    in address. That seems causing problem. The IORD/IOWR lines are simply ignored.

    Would you please take a look at my latest question regarding order of registers in

    SOPC component.

    Thanks a lot,

    =============== new question ================

    Hi,

    May be it is simple question, please confirm or answer:

    1. When I created a SOPC component(6 bit address, 32b data), the SOPC

    alocate 0xFF length of 32 bit memory.

    2. The order of all registers is the same as the order I claim register in

    verilog file. For example, the first claimed 32bit register has offset 0,

    the next one has offset 1.

    3. What if I have the mix types of register, 1 bit or 8 bit or 32 bit. How could

    I know the actual offset from the base.

    Thanks,

    ==========================================
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Hi,

    Being very simple, and perhaps working away from the real concepts, but what happends is somthing like this:

    The address space decoders (from the avalon switch fabric) always consider that you're addressig 32bit words. Your component's avalon interface receives a "chipselect" signal, generated using the "upper" address bits decoder output, a couple of read and write signals, and a set of "byte enable" signals (among a lot more signals). These "byte enable" signals are generated from the avalon addresses A1 and A0, so the addresses your component receives correspond to A2 (mapped to your A0), A3 (mapped to your A1), A4(mapped to your A2), and so on.

    If you try to access a register with offset (ofs) in your componet&#39;s address space, the real address you must access with the IOXXX macros is (ofs << 2).

    The macros IORD and IOWR do this mapping, but for 32 bit accesses. For accessing 8 and 16 bit registers you could use the macros IOXX_8DIRECT and IOXX_16DIRECT, specifying and offset left-shifted two times (multiplied by 4). Take a look at the alt_io.h header file.

    If your component requires to diferenciate from 8, 16 and 32 bits accesses you should consider using the byte enable signals in your registers decoding logic.