Forum Discussion
Altera_Forum
Honored Contributor
20 years agoBuilding user peripheral for Nios processor is not easy job, I guess you knew this quite well.
My suggestion will be: (1) make sure the Avalong bus interfacing is all right. (all standard bus signaling) (2) make sure your register file timing fits CPU's RD/WR operation. (3) Do ModelSim sim from IDE's hardware simulation. (Altera's AN351) Hope these will help,