problem in building a new SOPC component

Hi,

Being very simple, and perhaps working away from the real concepts, but what happends is somthing like this:

The address space decoders (from the avalon switch fabric) always consider that you're addressig 32bit words. Your component's avalon interface receives a "chipselect" signal, generated using the "upper" address bits decoder output, a couple of read and write signals, and a set of "byte enable" signals (among a lot more signals). These "byte enable" signals are generated from the avalon addresses A1 and A0, so the addresses your component receives correspond to A2 (mapped to your A0), A3 (mapped to your A1), A4(mapped to your A2), and so on.

If you try to access a register with offset (ofs) in your componet&#39;s address space, the real address you must access with the IOXXX macros is (ofs << 2).

The macros IORD and IOWR do this mapping, but for 32 bit accesses. For accessing 8 and 16 bit registers you could use the macros IOXX_8DIRECT and IOXX_16DIRECT, specifying and offset left-shifted two times (multiplied by 4). Take a look at the alt_io.h header file.

If your component requires to diferenciate from 8, 16 and 32 bits accesses you should consider using the byte enable signals in your registers decoding logic.