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Altera_Forum's avatar
Altera_Forum
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16 years ago

Powerdown Arria II in Chain Design

I'm designing a board with two Arria IIs on it. They will be configured

in Passive Serial Configuration as shown in page 9-23 of "Arria II GX Device Handbook Volume 1".

We may have just Device 1 running sometimes and leave Device 2 consuming

the least amount of power possible.

What is the recommended design to minimize Device 2 power consumption? Would somehow preventing the second device to be configure the best solution?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    If you're willing to have different regulators/converters for each FPGA, you can disable the outputs for the 2nd FPGA and thus, cut it's power supply.

    Reseting the device, by pulling the nCONFIG pin low, is problably the next most effective method.

    However, in either case, you'll have to re-configure the 2nd FPGA every time you "wake it up".

    In any case, you can also apply the usual techniques to reduce power consumption are

    a) use as low as possible clock frequencies

    b) make use of clock enables

    c) make use of gated clocks (beware of issues with gated clocks)

    d) power-down GX blocks
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Keeping PLLs in reset (assuming internal clocks are supplied by a PLL) should be sufficient to stop most clocked device activities.