Powerdown Arria II in Chain Design

If you're willing to have different regulators/converters for each FPGA, you can disable the outputs for the 2nd FPGA and thus, cut it's power supply.

Reseting the device, by pulling the nCONFIG pin low, is problably the next most effective method.

However, in either case, you'll have to re-configure the 2nd FPGA every time you "wake it up".

In any case, you can also apply the usual techniques to reduce power consumption are

a) use as low as possible clock frequencies

b) make use of clock enables

c) make use of gated clocks (beware of issues with gated clocks)

d) power-down GX blocks