PCI in uClinux

Hippo,

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originally posted by hippo@Mar 14 2006, 08:18 PM

i will post the driver for altera pci host bridge soon.

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Will that include the configuration stage as well?

And, how far are you? One of my customers is dying to see this. I'm perfectly willing to do a bit of work on this one, by the way.

Best regards,

Ben

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originally posted by bentwy+apr 21 2006, 08:02 pm--><div class='quotetop'>quote (bentwy @ apr 21 2006, 08:02 pm)</div>

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hippo,

<!--quotebegin-hippo@Mar 14 2006, 08:18 PM

i will post the driver for altera pci host bridge soon.

--- Quote End ---

Will that include the configuration stage as well?

And, how far are you? One of my customers is dying to see this. I&#39;m perfectly willing to do a bit of work on this one, by the way.

Best regards,

Ben

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=14552)</div>

[/b]

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please check step17 in this thread,

http://forum.niosforum.com/forum/index.php?showtopic=3174 (http://forum.niosforum.com/forum/index.php?showtopic=3174)

The PCI config is included.

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originally posted by bigboss25+apr 24 2006, 06:53 pm--><div class='quotetop'>quote (bigboss25 @ apr 24 2006, 06:53 pm)</div>

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originally posted by hippo@apr 22 2006, 10:03 am

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originally posted by bentwy@apr 21 2006, 08:02 pm

hippo,

<!--quotebegin-hippo@Mar 14 2006, 08:18 PM

i will post the driver for altera pci host bridge soon.

--- Quote End ---

Will that include the configuration stage as well?

And, how far are you? One of my customers is dying to see this. I&#39;m perfectly willing to do a bit of work on this one, by the way.

Best regards,

Ben

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=14552)</div>

[/b]

--- Quote End ---

please check step17 in this thread,

http://forum.niosforum.com/forum/index.php?showtopic=3174 (http://forum.niosforum.com/forum/index.php?showtopic=3174)

The PCI config is included.

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=14564)</div>

[/b]

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Hippo, do you mean that your driver will be written for Altera PCI Compiler 4.0 pci_mt_32 megafuntion ?

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=14597)</div>

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Yes, it is. I had the altera pci core in host bridge mode working on my boards.

Hi,

i have a custom board with the Altera PCI Compiler PCI Core in Host-Bridge-Mode and one Gigabit Ethernet Controller connected to the Bridge.

The Gigabit Ethernet Controller ist the Intel RC82540EM Ethernet Chip with Legal-PCI Bus.

I have fixed the ALTPCI.C-File and the Kernel detects the Ethernet Chip.

The Kernel says:

*******************snipp*******************************************

Autoconfig PCI channel 0x02157bd8

Scanning bus 00, I/O 0x86300000:0x86400000, Mem 0x86100000:0x86200000

00:01.0 Class 0200: 8086:100e (rev 02)

Mem at 0x86100000

I/O at 0x86300000

map slot 1 pin 1 irq 15

Setting IRQ for slot 0000:00:01.0 to 15

*******************Snapp*******************************************

As you see, the Intel Chip(Vendor 8086, Device 100E, Revision 2) was found on the PCI Bus. So i think the Bus-Hardware works fine...

The Ethernetchip then is attached to the Avalon-Addressspace and i can read and write the Configuration Space of the Ethernet Chip. (PCI-Base is 0x8600000, The Ethernetchip Configuration is then at 0x8600800). I can read and write it without problems....

But then, when the driver of the Ethernetchip (/NET/E1000) wants to setup the Ethernet Controller the Kernel says:

*******************snipp*******************************************

Intel® PRO/1000 Network Driver - version 6.3.9-k4

Copyright © 1999-2005 Intel Corporation.

ID: 34986200

PCI: Enable Device

PCI: Device is enabled...

e1000: 0000:00:01.0: e1000_probe: The EEPROM Checksum Is Not Valid

e1000: probe of 0000:00:01.0 failed with error -5

*******************Snapp*******************************************

The EeProm is programmed orrectly. But the Ethernetcontroller is not accessible over the Mem-Mapped Adress 0x86100000. The driver wants to access the first Control-Register at this address....

Wenn i read (with INL()) the Adresses i get:

*******************snipp*******************************************

Adresse: 0x86100000 Data: 0x100000

Adresse: 0x86100004 Data: 0x100004

Adresse: 0x86100008 Data: 0x100008

Adresse: 0x8610000c Data: 0x10000c

Adresse: 0x86100010 Data: 0x100010

Adresse: 0x86100014 Data: 0x100014

Adresse: 0x86100018 Data: 0x100018

Adresse: 0x8610001c Data: 0x10001c

Adresse: 0x86100020 Data: 0x100020

Adresse: 0x86100024 Data: 0x100024

Adresse: 0x86100028 Data: 0x100028

Adresse: 0x8610002c Data: 0x10002c

Adresse: 0x86100030 Data: 0x100030

Adresse: 0x86100034 Data: 0x100034

Adresse: 0x86100038 Data: 0x100038

Adresse: 0x8610003c Data: 0x10003c

*******************Snapp*******************************************

What is this? Anyone ideas? When i try to access the Controller over the I/O-Mapped-Space i get only the result 0x04 .... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/blink.gif

I hope anyone can help me....

Thankx

Marco

Up..

Maybe someone has Ideas?

Thanx

Marco

It looks like that the chip does not repsonse to memory acces.

So the access timeout.

Please use scope or LA, to look at pci bus lines, frame, irdy, trdy , ad[].

within a short pci memory registers access loop.

Check the altera pci core config page 4.

Try config the e1000 to a lower memory address in pci mmemory space,

and check the memory access.

You have to update altera pci core config page 4, avalon config,

change the pci base address of 32 bits memory page, to the value of avalon bus address assigned in sopc builder. ie, 86100000 in your case .

you should also update the io page mapping.

We want to use the same address mapping in both pci space and avalon space.

config space , pci base 0 , == avalon 86000000

mem space, pci base 86100000, == avalon 86100000

unused space?

io space, pci base 86300000, == avalon 86300000