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Honored ContributorParallel Flash memory access failed
Hello,
I am designing a simple system with a 4CE40 and a Spansion flash memory (S29GL512 : 64MB in 16bits organisation). But when I make a "hello world" software, it fails at "checking" step. Here are some more details : HARDWARE : - I use Quartus 11.0 toolkit. - the board is designed by me. The FPGA owns a NIOSII/e system with a tristate bridge and the CFI flash memory interface. Nothing else. - I checked the FPGA/memory connections, power supply etc ... => all OK - Nothing special during synthesys process, everything looks good. SOFTWARE : - I built a hello world project with Eclipse rev Helios Service Release 1 Build id: 20100917-0705. - I launch my soft with NiosII shell window using this command : bash-3.1$ nios2-download -g hello.elf && nios2-terminal - I get this answer : Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Pausing target processor: OK Initializing CPU cache (if present) OK Downloaded 29KB in 0.4s (72.5KB/s) Verifying 00001020 ( 0%) Verify failed between address 0x1020 and 0x122B Leaving target processor paused bash-3.1$ I think that the board has no problem (I tested each electrical connection between the FPGA and the flash). I tryed the same software with internal memory and it worked. There is a problem with the flash but I don't know where (SOPC system ? Compiler options ? ...) Please could anybody help me to anderstand ? Cyril19 Replies
Altera_ForumAre you trying to write to flash memory with the JTAG debugger??
That won't work. Neither can you use it for program data.- Altera_Forum
Hi dsl,
Thx for answering. Actually, there is a JTAG-UART in the system. It worked when I tryed the soft with internal memory. How am I supposed to proceed "normally" to write to the memory ? - Altera_Forum
Flash memory is effectively read-only memory that can be written to by very specific bus cycle sequences.
The memory datasheet will tell you how to write to it, and you might find some standard software that can do it. I'm also not sure how easy it is to perform the desired cycles through the normal bus width adapter that gets added between the 32bit Avalon bus and a 16bit memory. You can execute code from the flash (and have the cpu's reset vector addressing it), but you'll need other memory for data and stack and for the code running while you do the flash erases and writes. - Altera_Forum
Ok, I understand.
I just tried to add embeded RAM memory in SOPC. The pb is the same... I compared my design with a tutorial issued from DE1 Altera dev board. They use a 8bit data bus for their flash memory. But the components used in both SOPC designs are likely the same : NIOSII/e, tristated bridge, flash memory interface. But the flash interface versions looks different ... Can't CFI module program an external // flash memory ?? Do I need to use another specific tool to download my program in the flash device ? Thank you for your help ! - Altera_Forum
Please, anybody could help me ?
- Altera_Forum
Hello cyrill.garric,
I have the same problem. But only with quartus 10.1SP1. I used timing setup: 100ns wait 200ns hold 100ns. No good result:
What timing to you use? And is it working now? ThanksUsing cable "USB-Blaster ", device 1, instance 0x00 Resetting and pausing target processor: OK No CFI table found at address 0x00000000 Original contents (after writing 0xF0 and 0xFF to address 0x00000000): 0: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 10: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 20: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 30: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 40: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ Contents after writing 0x98 to address 0x000000AA: Same after writing 0x0098 to address 0x00000154: Same after writing 0x00000098 to address 0x000002A8: Same after writing 0x98 to address 0x00000055: Same after writing 0x0098 to address 0x000000AA: Same after writing 0x00000098 to address 0x00000154: Same after writing 0x98 to address 0x00000154: Same after writing 0x0098 to address 0x000002A8: Same after writing 0x00000098 to address 0x00000550: 0: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 10: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 20: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 30: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 40: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ Ignored possible autoselect code A8-A8 as no override data present in section Ignored possible autoselect code 09A8-09A8 as no override data present in section Leaving target processor paused - Altera_Forum
Hi Neptunus,
Actually, the flash device was dead. That was the root cause of my problem. After changing the device, my design worked normally. Here are the timings I used : Setup : 80ns Wait : 160ns Hold : 80ns But that timings depend on the flash device itself. In case you have a doubt, please have a look on its datasheet timings. Regards, Cyril - Altera_Forum--- Quote Start --- Hi Neptunus, Actually, the flash device was dead. That was the root cause of my problem. --- Quote End --- Hi Cyril, How did you end up programming your flash memory after you replaced the chip? Did you use the Flash Programmer that comes with Eclipse, or another method? Thanks.
- Altera_Forum
Hi fheineman,
I used the Altera program to test memories. I loaded the program to embeded RAM memory and simply runed it from Eclipse. But I guess I could also have used Flash Programmer. Cyril - Altera_Forum
hi cyril
Are you finished the project and working well with the flash? May you post the Qsys connections design!?
