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JLee25's avatar
JLee25
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2 years ago
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Nios V uC/TCP IP Failed

Hi support,

I am learning the simple socket server design on Cyclone 10 GX.

For unknown reason, the initialization process stopped with the error code (2010),

It's the TSE with DP83848.

The signals on MDIO and MDC is working.

Therefore I would like to know how to debug this issue.

Thank you.

BRs,

Johnson

Nios Cpu

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  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi


    I tried it on an Arria10 board. I think it should be okay if we migrate it over to the Cyclone10.

    Attached is my project for the Arria10.

    Let me try to migrate it to the Cyclone10 board and share u the project again.


    Regards

    Jingyang, Teh


  • JLee25's avatar
    JLee25
    Icon for Contributor rankContributor
    2 years ago

    Hi Jingyang,

    Thank you for the update.

    I hope to receive the C10 project soon.

    BRs,

    Johnson

  • JLee25's avatar
    JLee25
    Icon for Contributor rankContributor
    2 years ago

    Hi Jingyang,

    Do you have any update on the C10 project?

    Thank you.

  • JLee25's avatar
    JLee25
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    2 years ago

    Hi Jingyang,

    I just saw the update.

    After download the qar but I can't open it at Quartus Pro 23.2..

    By the way, what's the error code 20014 you mentioned?

    It's in my previous shared package?

    BRs,

    Johnson

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi Johnson

    Could you try with the latest 23.4 Quartus?

    I have migrated the latest NiosV example design to the cyclone10 gx board.

    I managed to solved the error code 20014.

    Now i am stuck with the same error code that you are facing. 2010

    Right now i am asking around what could be the cause for this.

    Regards

    Jingyang, Teh

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi

    I managed to get pass the error. It seems that in the previous design I did not connect the reset for the ethernet phy.

    Please find the latest project with the correct pin placement.

    You would need to assign these pin in the pin planner.

     

    Screenshot of the results

    Regards

    Jingyang, Teh

    • JLee25's avatar
      JLee25
      Icon for Contributor rankContributor
      2 years ago

      Hi Jungyang,

      Thank you for the update.

      Let me check on the C10 EVB and get back to you my finding later.

      BRs,

      Johnson

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi


    Did you managed to run the example design on the Cyclone10 EVB yet?

    Please note the following setting when trying to generate the BSP for the application.

    5.5.2.2. Configuring the BSP (intel.com)


    For the application you could reuse the application code from the latest design example.

    https://www.intel.com/content/www/us/en/design-example/776159/intel-arria-10-fpga-simple-socket-server-for-the-nios-v-m-processor-design-example.html


    Regards

    Jingyang, Teh


  • JLee25's avatar
    JLee25
    Icon for Contributor rankContributor
    2 years ago

    Hi Jingyang,

    Thank you for the link..

    I can see the example running now.

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi


    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    Regards

    Jingyang, Teh